公开(公告)号：US12153484B2

公开(公告)日：2024-11-26

申请号：US17941535

申请日：2022-09-09

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao

IPC: G06F1/3293 ,  G06F1/3215

Abstract: Aspects relate to limits management for a processor power distribution network. In an aspect, an electronic device has a processor with a processing core that is coupled to a power rail. The power rail is external to the processor. A current sensor is associated with the output of the power rail and configured to produce current sensor readings. A state-space unit is coupled to the current sensor. The state-space unit has a predictive model to apply the current sensor readings to the predictive model to predict a current budget for the processing core. A limit manager is configured to generate a current limit in response to the current budget. The limit manager limits a current draw of the processing core in response to the current limit.

公开(公告)号：US11157066B2

公开(公告)日：2021-10-26

申请号：US16690680

申请日：2019-11-21

Applicant: QUALCOMM Incorporated

Inventor： Byron Murphy ,  Rajeev Jain ,  Lipeng Cao ,  Harshat Pant

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3293

Abstract: A floorplan independent and cross-current free distributed adaptive power multiplexer (APM) is disclosed. In some implementations, an APM includes a first switch path coupled between a first voltage supply rail and an output terminal, the first switch path including a first switch; a second switch path coupled between a second voltage supply rail and the output terminal, the second switch path including a second switch, wherein the first switch and the second switch are configured to select one of a first voltage supply and a second voltage supply as an output voltage supply to be output at the voltage output terminal; and a comparator coupled to the first and the second voltage supply rails, and the voltage output terminal, wherein the comparator is configured to compare the output voltage supply with one of the first and the second voltage supplies and to output a control signal.

公开(公告)号：US10712807B2

公开(公告)日：2020-07-14

申请号：US15942207

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Byron Glenn Murphy ,  Lipeng Cao

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/3203

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

公开(公告)号：US20190302876A1

公开(公告)日：2019-10-03

申请号：US15942207

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Byron Glenn Murphy ,  Lipeng Cao

IPC: G06F1/32

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

公开(公告)号：US09990022B2

公开(公告)日：2018-06-05

申请号：US15199567

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Mong Chit Wong ,  Nam Dang ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Yu Huang ,  Lipeng Cao

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/263 ,  H01L23/50 ,  H02J1/08 ,  H02J1/108 ,  H02J9/061

Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

公开(公告)号：US09665160B1

公开(公告)日：2017-05-30

申请号：US15156859

申请日：2016-05-17

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Harshat Pant ,  Ramaprasath Vilangudipitchai

IPC: H03K3/356 ,  G06F1/32 ,  H03K3/3562 ,  H03K5/08 ,  G06F13/364

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F13/364 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/3562 ,  H03K5/08 ,  Y02D10/171

Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.