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    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER
    1.
    发明申请
    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER 有权
    在同步转换器上提供死区时间调整的电路和方法

    公开(公告)号：US20160118893A1

    公开(公告)日：2016-04-28

    申请号：US14918893

    申请日：2015-10-21

    Applicant: QUALCOMM Incorporated

    Inventor： James Thomas Doyle ,  Farsheed Mahmoudi ,  Chuang Zhang ,  Zhengming Fu ,  Sassan Shahrokhinia

    IPC: H02M3/158

    CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/157 ,  H02M2001/0012 ,  H02M2001/0048 ,  Y02B70/1491

    Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

    Abstract translation: 公开了一种用于在诸如同步降压转换器的电压调节器处有效地使用电力的装置和方法。 同步降压转换器包括分别由第一控制信号和第二控制信号操作的第一开关和第二开关，其中第一和第二控制信号具有相应的相位差。 逻辑电路针对第一控制信号和第二控制信号之间的相位差的迭代变化来测量输入脉宽调制（PWM）信号的占空比。 逻辑电路选择与PWM信号的最小值相对应的相位差，从而优化同步降压转换器的死区时间。 逻辑电路可以包括数字脉宽调制器。

    PRECISION BANDGAP REFERENCE
    4.
    发明申请
    PRECISION BANDGAP REFERENCE 审中-公开
    精密贴带参考

    公开(公告)号：US20160266598A1

    公开(公告)日：2016-09-15

    申请号：US14643981

    申请日：2015-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Mong Chit Wong ,  Nam Van Dang ,  Rajeev Jain ,  Bo-Ren Wang ,  Sassan Shahrokhinia

    IPC: G05F3/26

    CPC classification number: G05F3/267 ,  G05F3/30

    Abstract: Systems and methods for producing reference voltages are disclosed. An example bandgap reference circuit includes a core bandgap module that produces a bias control for biasing the gate of a transistor to produce a proportional to absolute temperature current. The core bandgap module may use an operational amplifier that uses auto-calibration to reduce its input offset voltage. A trimming module uses the bias control to produce a proportional to absolute temperature current that is combined with a trim current and supplied to a resistor and diode to produce a trimmed bandgap voltage. The trimmed bandgap voltage is buffered to produce a reference voltage output. The trim current may be set based on a room temperature measurement of the reference voltage output.

    Abstract translation: 公开了用于产生参考电压的系统和方法。 一个示例性带隙基准电路包括一个核心带隙模块，其产生用于偏置晶体管栅极以产生与绝对温度电流成比例的偏置控制。 核心带隙模块可以使用使用自动校准的运算放大器来减少其输入失调电压。 修整模块使用偏置控制来产生与绝缘温度电流成比例的结合微调电流并提供给电阻和二极管以产生修整的带隙电压。 修整的带隙电压被缓冲以产生参考电压输出。 可以基于参考电压输出的室温测量来设置微调电流。

    LINK LAYER TO PHYSICAL LAYER (PHY) SERIAL INTERFACE
    5.
    发明申请
    LINK LAYER TO PHYSICAL LAYER (PHY) SERIAL INTERFACE 有权
    连接层到物理层（PHY）串行接口

    公开(公告)号：US20150363349A1

    公开(公告)日：2015-12-17

    申请号：US14739439

    申请日：2015-06-15

    Applicant: QUALCOMM Incorporated

    Inventor： Terrence Brian Remple ,  Nam Van Dang ,  Sassan Shahrokhinia

    IPC: G06F13/42 ,  G06F13/38

    CPC classification number: G06F13/426 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0038 ,  G06F2213/3812

    Abstract: A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

    Abstract translation: 公开了到物理层（PHY）串行接口的链路层。 在一个方面，一种片上系统（SoC）集成电路（IC）包括链路层电路，并且远程IC包括通用串行总线（USB）PHY电路。 具有四条或更少线的总线连接两个IC。 链路桥与链路层电路通信，并将从链路层电路接收的USB收发器宏小区接口（UTMI）信号串行化为高速（HS）USB消息，以传输到远程IC。 链路桥接器还从远程IC上的USB PHY电路接收HS消息。 链路桥接反序列化HS消息以提取UTMI信令，并将提取的UTMI信令传递到链路层电路。

    Power multiplexing with an active load
    6.
    发明授权
    Power multiplexing with an active load 有权

    公开(公告)号：US10317968B2

    公开(公告)日：2019-06-11

    申请号：US15471692

    申请日：2017-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

    IPC: G06F1/26 ,  H02J1/08 ,  H02J1/10

    Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

    Adaptive power multiplexing with a power distribution network
    7.
    发明授权
    Adaptive power multiplexing with a power distribution network 有权

    公开(公告)号：US09990022B2

    公开(公告)日：2018-06-05

    申请号：US15199567

    申请日：2016-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Mong Chit Wong ,  Nam Dang ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Yu Huang ,  Lipeng Cao

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/263 ,  H01L23/50 ,  H02J1/08 ,  H02J1/108 ,  H02J9/061

    Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

    Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems
    8.
    发明授权
    Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems 有权

    公开(公告)号：US09684578B2

    公开(公告)日：2017-06-20

    申请号：US14527873

    申请日：2014-10-30

    Applicant: QUALCOMM Incorporated

    Inventor： Terrence Brian Remple ,  Duane Eugene Ellis ,  Sassan Shahrokhinia ,  Victor Kam Kin Wong

    IPC: G06F11/00 ,  G06F11/22 ,  G06F11/263 ,  G06F11/267

    CPC classification number: G06F11/221 ,  G06F11/263 ,  G06F11/267

    Abstract: Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function.

    Power Multiplexing with an Active Load
    9.
    发明申请
    Power Multiplexing with an Active Load 审中-公开

    公开(公告)号：US20180284859A1

    公开(公告)日：2018-10-04

    申请号：US15471692

    申请日：2017-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

    IPC: G06F1/26

    CPC classification number: G06F1/263 ,  H02J1/08 ,  H02J1/108

    Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

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