公开(公告)号：US20140281391A1

公开(公告)日：2014-09-18

申请号：US13827867

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： James Norris Dieffenderfer ,  Michael William Morrow ,  Rodney Wayne Smith ,  Jeffery M. Schottmiller ,  Daniel S. Higdon ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Kulin N. Kothari

IPC: G06F9/30

Abstract: A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.

Abstract translation: 解码将立即数移动（复制或写入）到结构化寄存器的移动即时指令时，在缓存中存储恒定值（立即数或立即数）的处理器。 常量值存储在缓存中的条目中。 缓存中的每个条目包括一个字段，用于指示其存储的常量值是否有效，以及一个字段，用于将条目与架构化寄存器相关联。 一旦常数值被存储在高速缓存中，则立即可以转发到处理器流水线，其中解码的指令可能需要常数值作为操作数。

公开(公告)号：US20140047221A1

公开(公告)日：2014-02-13

申请号：US13788008

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew S. Irwin ,  James Norris Dieffenderfer ,  Melinda J. Brown ,  Jeffery M. Schottmiller ,  Brian Michael Stempel ,  Michael Scott McIlvaine ,  Rodney Wayne Smith ,  Michael William Morrow

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30072

Abstract: Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中对产生标记和标记消息的指令进行融合。 在一个实施例中，指令处理电路在指令流中检测指示产生第一标志结果的第一操作的标志产生指令。 指令处理电路还检测指示流中指示消耗第一标志结果的第二操作的指令消息指令作为输入。 指令处理电路产生指示第一操作的融合指令，该第一操作产生第一标志结果并指示第二操作消耗第一标志结果作为输入。 以这种方式，作为非限制性示例，融合指令消除了标志产生指令和标志消耗指令之间的写后读取危险的可能性。

公开(公告)号：US20130311754A1

公开(公告)日：2013-11-21

申请号：US13676146

申请日：2012-11-14

Applicant: QUALCOMM INCORPORATED

Inventor： Melinda J. Brown ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Rodney Wayne Smith ,  Jeffrey M. Schottmiller ,  Andrew S. Irwin ,  Michael William Morrow

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3017

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中具有相反条件的条件写指令。 在一个实施例中，由指令处理电路检测基于评估第一条件将第一值写入目标寄存器的第一条件写入指令。 该电路还基于评估与第一条件逻辑相反的第二条件，检测向目标寄存器写入第二值的第二条件写入指令。 选择第一个条件或第二个条件作为融合指令条件，并将相应的值选为if-true和if-false值。 如果融合指令条件评估为真，则生成融合指令，以便如果融合指令条件评估为真，则将if-true值有选择地写入目标寄存器，如果融合指令条件评估为false，则选择性地将if-false值写入目标寄存器。

公开(公告)号：US11593117B2

公开(公告)日：2023-02-28

申请号：US16024725

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Harsh Thakker ,  Thomas Philip Speier ,  Rodney Wayne Smith ,  Kevin Jaget ,  James Norris Dieffenderfer ,  Michael Morrow ,  Pritha Ghoshal ,  Yusuf Cagatay Tekmen ,  Brian Stempel ,  Sang Hoon Lee ,  Manish Garg

IPC: G06F9/38 ,  G06F9/30

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

公开(公告)号：US10108417B2

公开(公告)日：2018-10-23

申请号：US14860032

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Rodney Wayne Smith ,  Sandeep Suresh Navada ,  Shivam Priyadarshi ,  Raguram Damodaran

IPC: G06F9/30 ,  G06F9/38

Abstract: Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor (OoP) is provided. An OoP is provided that includes an instruction processing system. The instruction processing system includes a number of instruction processing stages configured to pipeline the processing and execution of instructions according to a dataflow execution. The instruction processing system also includes a register map table (RMT) configured to store address pointers mapping logical registers to physical registers in a physical register file (PRF) for storing produced data for use by consumer instructions without overwriting logical registers for later executed, out-of-order instructions. In certain aspects, the instruction processing system is configured to write back (i.e., store) narrow values produced by executed instructions directly into the RMT, as opposed to writing the narrow produced values into the PRF in a write back stage.

公开(公告)号：US09851774B2

公开(公告)日：2017-12-26

申请号：US14986738

申请日：2016-01-04

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran ,  Jeffrey Todd Bridges ,  Ryan Wells ,  Norman Gargash ,  Rodney Wayne Smith

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US20170192484A1

公开(公告)日：2017-07-06

申请号：US14986738

申请日：2016-01-04

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Anil Krishna ,  Raguram Damodaran ,  Jeffrey Todd Bridges ,  Ryan Wells ,  Norman Gargash ,  Rodney Wayne Smith

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US11669333B2

公开(公告)日：2023-06-06

申请号：US15963126

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Rodney Wayne Smith ,  Raghavan Madhavan ,  Luke Yen ,  Shivam Priyadarshi ,  Yusuf Cagatay Tekmen

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3802

Abstract: In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

公开(公告)号：US20190294443A1

公开(公告)日：2019-09-26

申请号：US15926429

申请日：2018-03-20

Applicant: QUALCOMM Incorporated

Inventor： Sandeep Suresh Navada ,  Michael Scott McIlvaine ,  Rodney Wayne Smith ,  Robert Douglas Clancy ,  Yusuf Cagatay Tekmen ,  Niket Choudhary ,  Daren Eugene Streett ,  Richard Doing ,  Ankita Upreti

IPC: G06F9/38

Abstract: Providing early pipeline optimization of conditional instructions in processor-based systems is disclosed. In one aspect, an instruction pipeline of a processor-based system detects a mispredicted branch (i.e., following a misprediction of a condition associated with a speculatively executed conditional branch instruction), and records a current state of one or more condition flags as a condition flags snapshot. After a pipeline flush is initiated and a corrected fetch path is restarted, an instruction decode stage of the instruction pipeline uses the condition flags snapshot to apply optimizations to conditional instructions detected within the corrected fetch path. According to some aspects, the condition flags snapshot is subsequently invalidated upon encountering a condition-flag-writing instruction within the corrected fetch path. In this manner, the condition flags snapshot enables non-speculative (with respect to the corrected fetch path) resolution of conditional instructions earlier within the instruction pipeline, thus conserving system resources and improving processor performance.

公开(公告)号：US09411590B2

公开(公告)日：2016-08-09

申请号：US13833844

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Rodney Wayne Smith ,  Jeffery M. Schottmiller ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Melinda J. Brown ,  Daren Eugene Streett

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30054 ,  G06F9/3806

Abstract: An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.

Abstract translation: 一种用于通过利用链路寄存器堆栈在处理器中执行呼叫分支和返回分支指令的装置和方法。 处理器包括初始化为零的分支计数器，并且每当处理器解码除了呼叫转移指令之外的链接寄存器操作指令时，该分支计数器被设置为零。 每当一个呼叫转移指令被解码并且一个地址被推到链路寄存器堆栈上时，分支计数器递增1。 响应于解码返回分支指令并且提供的分支计数器不为零，解码的返回分支指令的目标地址从链接寄存器堆栈中弹出，分支计数器递减，并且不需要检查目标地址 为正确。