公开(公告)号：US20190273116A1

公开(公告)日：2019-09-05

申请号：US16116744

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Stephen Alan FANELLI ,  Yun Han CHU

IPC: H01L27/20 ,  H03H9/05 ,  H03H9/56 ,  H03H9/64 ,  H03H3/02 ,  H03H3/08

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

公开(公告)号：US20190214506A1

公开(公告)日：2019-07-11

申请号：US15865117

申请日：2018-01-08

Applicant: QUALCOMM Incorporated

Inventor： Plamen Vassilev KOLEV ,  Sinan GOKTEPELI ,  Peter Graeme CLARKE

IPC: H01L29/86 ,  H01L29/06 ,  H01L23/552 ,  H01L23/528 ,  H01L21/02 ,  H01L29/66

Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.

公开(公告)号：US20180083098A1

公开(公告)日：2018-03-22

申请号：US15272335

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI

IPC: H01L29/06 ,  H01L27/12 ,  H01L23/66 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L29/0649 ,  H01L21/7624 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1218 ,  H01L2223/6616

Abstract: A substrate is provided with at least one etch stop layer to line a cavity after etching of the substrate. The cavity isolates the substrate from an active layer including a plurality of transistors.

公开(公告)号：US20170373026A1

公开(公告)日：2017-12-28

申请号：US15189893

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI

IPC: H01L23/66 ,  H01L29/10

CPC classification number: H01L23/66 ,  H01L21/76898 ,  H01L23/5225 ,  H01L27/1464 ,  H01L41/09 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2924/1421

Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device.

公开(公告)号：US20210242322A1

公开(公告)日：2021-08-05

申请号：US16778546

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/40

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

公开(公告)号：US20200235107A1

公开(公告)日：2020-07-23

申请号：US16742886

申请日：2020-01-14

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Sivakumar KUMARASAMY

IPC: H01L27/112 ,  G11C17/16 ,  G11C17/18

Abstract: Antifuse memory cells as well as other applications may provide advantages of conventional approaches. In some examples, a metal backside gate or contact may be formed in the insulator layer opposite the front side contacts and circuits. The metal backside gate or contact may allow a higher voltage on a low resistance and capacitance lie to be applied directly to the dielectric layer of the antifuse to more quickly breakdown the dielectric and program the antifuse.

公开(公告)号：US20200185522A1

公开(公告)日：2020-06-11

申请号：US16788197

申请日：2020-02-11

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Ravi Pramod Kumar VEDULA ,  Sivakumar KUMARASAMY ,  George Pete IMTHURN ,  Sinan GOKTEPELI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L21/762 ,  H01L21/28

Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

公开(公告)号：US20190371890A1

公开(公告)日：2019-12-05

申请号：US15993679

申请日：2018-05-31

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Yun Han CHU ,  Qingqing LIANG

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/45 ,  H01L21/84 ,  H01L21/74 ,  H01L21/285

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

公开(公告)号：US20190326401A1

公开(公告)日：2019-10-24

申请号：US15958792

申请日：2018-04-20

Applicant: QUALCOMM Incorporated

Inventor： Plamen Vassilev KOLEV ,  Sinan GOKTEPELI ,  Peter Graeme CLARKE

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66

Abstract: In certain aspects, a silicon-on-insulator device comprises a back insulating layer and a semiconductor layer on the back insulating layer. The semiconductor layer includes a source region of a first conductive type having a front source surface and a back source surface, a channel region of a second conductive type have a front channel surface and a back channel surface, and a drain region of the first conductive type. The silicon-on-insulator device further comprises a gate insulating layer on the front channel surface of the channel region and a back silicidation layer on at least a portion of the back source surface and a portion of back channel surface.

公开(公告)号：US20190109570A1

公开(公告)日：2019-04-11

申请号：US15959562

申请日：2018-04-23

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Sinan GOKTEPELI ,  George Pete IMTHURN

IPC: H03F3/195 ,  H01L23/66 ,  H03F1/26 ,  H03F3/193 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092

Abstract: A radio frequency integrated circuit (RFIC) includes multi-finger transistors including discrete diffusion regions and interconnected within a reconfigured form factor as a single switch transistor. The RFIC also includes a source bus having a first plurality of source fingers coupled to each source region of the multi-finger transistors and a second plurality of source fingers orthogonally coupled to the first plurality of source fingers. The second plurality of source fingers couple the discrete diffusion regions in parallel. The RFIC also includes a drain bus having a first plurality of drain fingers coupled to each drain region of the multi-finger transistors and a second plurality of drain fingers orthogonally coupled to the first plurality of drain fingers. The second plurality of drain fingers electrically couple the discrete diffusion regions in parallel. The RFIC further includes a plurality of interconnected body contacts to bias a body of each of the multi-finger transistors.