公开(公告)号：US11961800B2

公开(公告)日：2024-04-16

申请号：US17814152

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/07 ,  H01L25/075 ,  H01L33/00 ,  H01L33/38 ,  H01L33/62 ,  H01L21/321 ,  H01L33/06 ,  H01L33/32

CPC classification number: H01L23/5226 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/11 ,  H01L24/89 ,  H01L25/072 ,  H01L25/0753 ,  H01L33/0093 ,  H01L33/38 ,  H01L33/62 ,  H01L21/3212 ,  H01L24/81 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/08225 ,  H01L2224/08501 ,  H01L2224/80006 ,  H01L2224/80815 ,  H01L2224/80895 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

公开(公告)号：US11955349B2

公开(公告)日：2024-04-09

申请号：US17809932

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chien Ling Hwang

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/11 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/11002

Abstract: A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.

公开(公告)号：US11670609B2

公开(公告)日：2023-06-06

申请号：US17178491

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chen ,  Ching-Tien Su

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L25/10 ,  H01L23/31 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/03 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/485 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1146 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/3512

Abstract: A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

公开(公告)号：US20190198456A1

公开(公告)日：2019-06-27

申请号：US16289561

申请日：2019-02-28

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： David T. PETZOLD ,  David Scott WHITEFIELD

IPC: H01L23/00 ,  H03H9/24 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L23/66 ,  H01L21/764 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/786 ,  H01L29/66 ,  H01L27/20 ,  H01L21/762 ,  H03H9/02 ,  H04B1/40 ,  H01L23/528 ,  H01L49/02 ,  H04B1/44 ,  H01L23/535 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/764 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3121 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L27/1203 ,  H01L27/20 ,  H01L28/10 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2223/6677 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15313 ,  H03H9/02566 ,  H03H9/24 ,  H04B1/40 ,  H04B1/44 ,  H01L2224/45099

Abstract: A method for fabricating a semiconductor die involves providing a semiconductor substrate, forming a plurality of active devices and a plurality of passive devices over the semiconductor substrate, forming one or more electrical connections to the plurality of active devices and the plurality of passive devices, forming one or more dielectric layers over at least a portion of the electrical connections, applying an interface material over at least a portion of the one or more dielectric layers, removing portions of the interface material to form a plurality of trenches, and covering at least a portion of the interface material and the plurality of trenches with a substrate layer to form a plurality of radio-frequency isolation cavities.

公开(公告)号：US20180211830A1

公开(公告)日：2018-07-26

申请号：US15841946

申请日：2017-12-14

Applicant: Hoyoung Kim ,  Hyo-Sun Lee ,  Soojin Kim ,  Keonyoung Kim ,  Jinhye Bae ,  Hoon Han ,  Tae Soo Kwon ,  Jung Hun Lim

Inventor： Hoyoung Kim ,  Hyo-Sun Lee ,  Soojin Kim ,  Keonyoung Kim ,  Jinhye Bae ,  Hoon Han ,  Tae Soo Kwon ,  Jung Hun Lim

IPC: H01L21/02 ,  C11D7/26 ,  C11D7/08 ,  C11D7/32 ,  C11D11/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/02068 ,  C11D7/08 ,  C11D7/261 ,  C11D7/264 ,  C11D7/266 ,  C11D7/3209 ,  C11D7/3218 ,  C11D11/0047 ,  H01L21/02057 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2224/11 ,  H01L2224/03

Abstract: Embodiments of the inventive concepts provide a method of manufacturing a semiconductor device and a cleaning composition for an adhesive layer. The method includes preparing a semiconductor substrate to which an adhesive layer adheres, removing the adhesive layer from the semiconductor substrate, and applying a cleaning composition to the semiconductor substrate to remove a residue of the adhesive layer. The cleaning composition includes a solvent including a ketone compound and having a content that is equal to or greater than 40 wt % and less than 90 wt %, quaternary ammonium salt, and primary amine.

公开(公告)号：US09978717B2

公开(公告)日：2018-05-22

申请号：US15261402

申请日：2016-09-09

Applicant: THRUCHIP JAPAN INC.

Inventor： Tadahiro Kuroda

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L23/538 ,  H01L23/64 ,  H01L21/683 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06 ,  H01L27/092 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/18 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

Abstract: The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

公开(公告)号：US20180068920A1

公开(公告)日：2018-03-08

申请号：US15259063

申请日：2016-09-08

Applicant: Nexperia B.V.

Inventor： Chi Ho Leung ,  Pompeo V. Umali ,  Shun Tik Yeung ,  Kan Wae Lam

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L21/288

CPC classification number: H01L23/3114 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/83 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/0615 ,  H01L2224/10145 ,  H01L2224/26145 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/83

Abstract: A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.

公开(公告)号：US09881851B2

公开(公告)日：2018-01-30

申请号：US15062002

申请日：2016-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kengo Uchida

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/03002 ,  H01L2224/03005 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03831 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a semiconductor substrate, a device layer located at an upper surface of the semiconductor substrate, an insulating layer located on the device layer, and a through electrode. The through electrode includes a body located in a through hole provided in the insulating layer and a head located on the body and the insulating layer and is electrically connected to an upper-layer wiring in the device layer. A perimeter of the head on a lower surface side thereof is smaller than a perimeter of the head on an upper surface side thereof.

公开(公告)号：US09865524B2

公开(公告)日：2018-01-09

申请号：US14222547

申请日：2014-03-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Chang Beom Yong ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/66

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

公开(公告)号：US09859225B2

公开(公告)日：2018-01-02

申请号：US15154817

申请日：2016-05-13

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： David T. Petzold ,  David Scott Whitefield

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/50 ,  G01N27/414 ,  H01L23/00 ,  H01L27/12 ,  H01L21/84 ,  H01L23/66 ,  H03H9/24 ,  H01L21/764 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78 ,  H04B1/40 ,  H01L21/306 ,  H01L23/535 ,  H01L29/786 ,  H04B1/44 ,  H01L21/683 ,  H01L25/16 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/764 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3121 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L27/1203 ,  H01L27/20 ,  H01L28/10 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/786 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2223/6677 ,  H01L2224/03 ,  H01L2224/03002 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15313 ,  H03H9/02566 ,  H03H9/24 ,  H04B1/40 ,  H04B1/44 ,  H01L2224/45099

Abstract: Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.