公开(公告)号：US09576937B2

公开(公告)日：2017-02-21

申请号：US15130721

申请日：2016-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： Michael A. Stuber ,  Stuart B. Molin

IPC: H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/80006 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/83

Abstract: An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together.

Abstract translation: 集成电路组件包括第一衬底和第二衬底，其中有源层形成在每个衬底的第一表面上，并且每个衬底的第二表面耦合在一起。 制造集成电路组件的方法包括在两个基板中的每一个的第一表面上形成有源层，并将基板的第二表面联接在一起。

公开(公告)号：US09530796B2

公开(公告)日：2016-12-27

申请号：US14272261

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Chris Brindle

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.

Abstract translation: 集成电路组件包括绝缘层，半导体层，手柄层，金属互连层和晶体管。 绝缘层具有第一表面，第二表面和从第一表面延伸到第二表面的孔。 半导体层具有第一表面和第二表面，半导体层的第一表面与绝缘层的第一表面接触。 手柄层耦合到半导体层的第二表面。 金属互连层耦合到绝缘层的第二表面，金属互连层设置在绝缘层的孔内。 晶体管位于半导体层中。 绝缘层中的孔至少延伸到半导体层的第一表面。 金属互连层将多个晶体管彼此电耦合。

公开(公告)号：US09496227B2

公开(公告)日：2016-11-15

申请号：US14707998

申请日：2015-05-08

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Paul A. Nygaard ,  Michael A. Stuber

IPC: H01L21/78 ,  H01L23/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L23/36 ,  H01L23/367 ,  H01L29/786 ,  H01L23/66

CPC classification number: H01L23/562 ,  H01L21/7624 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The excavated region covers a majority of the signal-processing region of the integrated circuit.

Abstract translation: 在一个实施例中，公开了一种具有信号处理区域的集成电路。 集成电路包括从绝缘体上硅晶片上分离的绝缘体上硅芯片。 绝缘体上的芯片包括有源层，绝缘体层，衬底和强化层。 衬底由挖掘的衬底区域和支撑区域组成，支撑区域与绝缘体层接触。 挖掘区域覆盖集成电路的信号处理区域的大部分。