公开(公告)号：US10217822B2

公开(公告)日：2019-02-26

申请号：US15241359

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard ,  Stuart B Molin ,  Michael A Stuber ,  Max Aubain

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/367 ,  H01L29/786 ,  H01L27/12 ,  H01L23/00 ,  H01L21/762

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

公开(公告)号：US20160359002A1

公开(公告)日：2016-12-08

申请号：US15241359

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber ,  Max Aubain

IPC: H01L29/10 ,  H01L23/367 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78654 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03845 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract translation: 本发明的实施例提供了使用应变层的半导体结构中的晶体管的增强。 该结构包括由挖掘区域和图案区域构成的图案层，位于挖掘区域和图案区域上的应变层，位于应变层上方的有源层，形成在有源层中的场效应晶体管，以及 位于有源层上方的手柄层。 场效应晶体管包括源极，漏极和沟道。 通道完全位于图案区域的横向范围内。 源极和漏极各自仅部分地位于图案区域的横向范围内。 应变层改变通道的载流子迁移率。 在一些实施例中，将应变层引入到绝缘体上半导体结构的背面。

公开(公告)号：US09502433B2

公开(公告)日：2016-11-22

申请号：US14929206

申请日：2015-10-30

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L27/06 ,  H01L27/07

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0727 ,  H01L29/47 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7839 ,  H01L29/78615

Abstract: Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating.

公开(公告)号：US09496270B2

公开(公告)日：2016-11-15

申请号：US14292395

申请日：2014-05-30

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard

IPC: H01L23/525 ,  H01L27/112 ,  H01L21/8234 ,  G11C17/16 ,  H01L21/84 ,  H01L27/12 ,  H01L29/861

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/1203 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate insulator. The memory cell also comprises a bulk region of a first conductivity type in contact with a first side of the thin gate insulator. The memory cell also comprises a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator. The memory cell also comprises a source region of a second conductivity type in contact with the bulk region at a junction. The polysilicon gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator. The junction forms a diode for the memory cell. The bulk region can be in an active layer of a semiconductor on insulator structure.

Abstract translation: 公开了涉及单晶体​​二极管连接的反熔丝存储器单元的各种方法和装置。 示例性的存储单元包括薄栅极绝缘体。 存储单元还包括与薄栅极绝缘体的第一侧接触的第一导电类型的主体区域。 存储单元还包括与薄栅极绝缘体的第二侧接触的第一导电类型的多晶硅栅电极。 存储单元还包括在接合处与主体区域接触的第二导电类型的源极区域。 多晶硅栅电极和源极区域可操作地耦合到编程电压源，该编程电压源通过吹薄栅极绝缘体来寻址存储单元。 接点形成用于存储单元的二极管。 体区域可以是绝缘体上半导体结构的有源层。

公开(公告)号：US09780117B2

公开(公告)日：2017-10-03

申请号：US14521327

申请日：2014-10-22

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/84 ,  H01L27/06 ,  H01L29/10 ,  H01L29/32 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/32053 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66477 ,  H01L29/7839 ,  H01L29/78612 ,  H01L29/872

Abstract: A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.

公开(公告)号：US09496227B2

公开(公告)日：2016-11-15

申请号：US14707998

申请日：2015-05-08

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Paul A. Nygaard ,  Michael A. Stuber

IPC: H01L21/78 ,  H01L23/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L23/36 ,  H01L23/367 ,  H01L29/786 ,  H01L23/66

CPC classification number: H01L23/562 ,  H01L21/7624 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The excavated region covers a majority of the signal-processing region of the integrated circuit.

Abstract translation: 在一个实施例中，公开了一种具有信号处理区域的集成电路。 集成电路包括从绝缘体上硅晶片上分离的绝缘体上硅芯片。 绝缘体上的芯片包括有源层，绝缘体层，衬底和强化层。 衬底由挖掘的衬底区域和支撑区域组成，支撑区域与绝缘体层接触。 挖掘区域覆盖集成电路的信号处理区域的大部分。