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公开(公告)号：US10389315B2
公开(公告)日：2019-08-20
申请号：US15912170
申请日：2018-03-05
Applicant: QUALCOMM Incorporated
Inventor： Chulkyu Lee , Shih-Wei Chou , Ying Duan
Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor.
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公开(公告)号：US09496879B1
公开(公告)日：2016-11-15
申请号：US14842644
申请日：2015-09-01
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Chulkyu Lee , Shih-Wei Chou , Harry Dang , Ohjoon Kwon
CPC classification number: H03L7/0807 , H03L7/0812 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L7/04 , H04L25/4917
Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.
Abstract translation: 公开了通过多线，多相接口进行数据通信的方法，装置和系统。 一种数据通信方法包括配置时钟恢复电路以提供第一时钟信号，该第一时钟信号包括在接口上发送的每个符号的脉冲，其中符号以第一频率在接口上发送，调整时钟恢复电路的环路延迟 修改第一时钟以具有不超过第一频率的一半的第二频率，其中时钟恢复电路在第一时钟信号中产生用于整数符号中的第一个的脉冲，并且抑制其他符号的脉冲产生 整数个符号，配置时钟发生电路以提供第二时钟信号，以及使用第一时钟信号和第二时钟信号从接口捕获符号。
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公开(公告)号：US09485080B1
公开(公告)日：2016-11-01
申请号：US14842610
申请日：2015-09-01
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Chulkyu Lee , Harry Dang , Ohjoon Kwon
CPC classification number: H04L7/0008 , H03K5/135 , H04L5/0048 , H04L7/033 , H04L7/04 , H04L7/08 , H04L25/0272 , H04L25/4923
Abstract: Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.
Abstract translation: 公开了用于时钟校准的方法，装置和系统。 一种用于时钟数据恢复电路校准的方法包括配置第一时钟恢复电路以提供具有第一频率的时钟信号，并且对于在3线3相接口上传输的每个符号包括单个脉冲，并且校准第一频率 时钟恢复电路，通过逐渐增加由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有小于第一频率的频率，并且当第一时钟恢复电路具有 小于第一频率的频率，逐渐减小由第一时钟恢复电路的延迟元件提供的延迟周期，直到由第一时钟恢复电路提供的时钟信号具有与第一频率匹配的频率。
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公开(公告)号：US09401731B2
公开(公告)日：2016-07-26
申请号：US14722271
申请日：2015-05-27
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Harry Huy Dang , Chulkyu Lee
CPC classification number: H04B1/0475 , H04B3/30 , H04B15/02 , H04L25/028 , H04L25/03878
Abstract: Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.
Abstract translation: 在详细描述中公开的方面包括用于三相通信的偏斜控制。 三相通信涉及三个信号分支。 当一个信号分支耦合到共模电压而另一个信号分支与共模电压分离时，可能发生信号偏移。 在这方面，在一个方面，在耦合到共模电压的信号支路中引入阻抗失配，以帮助向左偏移信号偏移的最右边的交叉。 在另一方面，电流源或电流吸收器耦合到信号分支与共模电压分离，以帮助向右偏移信号偏移的最左边的交叉。 通过向右移动最左边的交叉点，向右移动最左边的交叉点，可以减少信号偏移，从而导致三相通信中的抖动减小和数据完整性的改善。
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公开(公告)号：US11411711B2
公开(公告)日：2022-08-09
申请号：US17305542
申请日：2021-07-09
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Jing Wu , Shih-Wei Chou
Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.
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Patent Agency Ranking
公开(公告)号：US11349445B2
公开(公告)日：2022-05-31
申请号：US17017239
申请日：2020-09-10
Applicant: QUALCOMM Incorporated
Abstract: A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.
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17.发明授权公开(公告)号：US10298381B1
公开(公告)日：2019-05-21
申请号：US15967434
申请日：2018-04-30
Applicant: QUALCOMM Incorporated
Inventor： Chulkyu Lee , Shih-Wei Chou , Ying Duan
IPC: H04L7/00
Abstract: Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.
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公开(公告)号：US20180358939A1
公开(公告)日：2018-12-13
申请号：US15912170
申请日：2018-03-05
Applicant: QUALCOMM Incorporated
Inventor： Chulkyu Lee , Shih-Wei Chou , Ying Duan
CPC classification number: H03F3/2178 , H03F1/0244 , H03F1/0277 , H03F3/211 , H03F3/45197 , H04B1/06
Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor
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公开(公告)号：US20150381218A1
公开(公告)日：2015-12-31
申请号：US14722271
申请日：2015-05-27
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Harry Huy Dang , Chulkyu Lee
CPC classification number: H04B1/0475 , H04B3/30 , H04B15/02 , H04L25/028 , H04L25/03878
Abstract: Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.
Abstract translation: 在详细描述中公开的方面包括用于三相通信的偏斜控制。 三相通信涉及三个信号分支。 当一个信号分支耦合到共模电压而另一个信号分支与共模电压分离时，可能发生信号偏移。 在这方面，在一个方面，在耦合到共模电压的信号支路中引入阻抗失配，以帮助向左偏移信号偏移的最右边的交叉。 在另一方面，电流源或电流吸收器耦合到信号分支与共模电压分离，以帮助向右偏移信号偏移的最左边的交叉。 通过向右移动最左边的交叉点，向右移动最左边的交叉点，可以减少信号偏移，从而导致三相通信中的抖动减小和数据完整性的改善。
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公开(公告)号：US11095425B2
公开(公告)日：2021-08-17
申请号：US17001801
申请日：2020-08-25
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Jing Wu , Shih-Wei Chou
Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.
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