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    C-PHY data-triggered edge generation with intrinsic half-rate operation
    1.
    发明授权
    C-PHY data-triggered edge generation with intrinsic half-rate operation 有权

    公开(公告)号：US11327914B1

    公开(公告)日：2022-05-10

    申请号：US17162497

    申请日：2021-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Da Ying ,  Shih-Wei Chou ,  Ying Duan ,  Abhay Dixit

    IPC: G06F13/20 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.

    C-PHY half-rate wire state encoder and decoder
    2.
    发明授权
    C-PHY half-rate wire state encoder and decoder 有权

    公开(公告)号：US11240077B2

    公开(公告)日：2022-02-01

    申请号：US17070219

    申请日：2020-10-14

    Applicant: QUALCOMM Incorporated

    Inventor： Chulkyu Lee ,  Ying Duan ,  Shih-Wei Chou

    IPC: H04L25/49 ,  H04L25/493 ,  H04L7/00 ,  H04L25/14 ,  H04L25/02

    Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

    MIPI D-PHY receiver auto rate detection and high-speed settle time control
    3.
    发明授权
    MIPI D-PHY receiver auto rate detection and high-speed settle time control 有权

    公开(公告)号：US11023409B2

    公开(公告)日：2021-06-01

    申请号：US16591719

    申请日：2019-10-03

    Applicant: QUALCOMM Incorporated

    Inventor： Yasser Ahmed ,  Ying Duan ,  Shih-Wei Chou

    IPC: G06F13/42

    Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.

    LOW POWER PHYSICAL LAYER DRIVER TOPOLOGIES
    4.
    发明申请
    LOW POWER PHYSICAL LAYER DRIVER TOPOLOGIES 审中-公开

    公开(公告)号：US20180234122A1

    公开(公告)日：2018-08-16

    申请号：US15950779

    申请日：2018-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shih-Wei Chou ,  Chulkyu Lee ,  Dhaval Sejpal

    IPC: H04B1/04 ,  H04L25/493 ,  H04L25/02 ,  H04B3/52 ,  G06F13/40

    CPC classification number: H04B1/04 ,  G06F13/4072 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/493

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.

    Small loop delay clock and data recovery block for high-speed next generation C-PHY
    5.
    发明授权
    Small loop delay clock and data recovery block for high-speed next generation C-PHY 有权

    公开(公告)号：US11095425B2

    公开(公告)日：2021-08-17

    申请号：US17001801

    申请日：2020-08-25

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Jing Wu ,  Shih-Wei Chou

    IPC: H04B3/00 ,  H04L25/00 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

    Low power physical layer driver topologies
    6.
    发明授权
    Low power physical layer driver topologies 有权

    公开(公告)号：US10833899B2

    公开(公告)日：2020-11-10

    申请号：US16526332

    申请日：2019-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Shih-Wei Chou ,  Chulkyu Lee ,  Dhaval Sejpal

    IPC: H04L25/02 ,  H04L25/493 ,  G06F13/40 ,  H04B1/04 ,  H04B3/52

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

    Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
    8.
    发明授权
    Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface 有权

    公开(公告)号：US10333690B1

    公开(公告)日：2019-06-25

    申请号：US15971016

    申请日：2018-05-04

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Abhay Dixit ,  Shih-Wei Chou ,  Chulkyu Lee

    IPC: H04L7/033 ,  H04L7/00 ,  G09G5/00 ,  H04L25/49

    Abstract: Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

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