公开(公告)号：US11264995B1

公开(公告)日：2022-03-01

申请号：US17079795

申请日：2020-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Chao ,  Yiwu Tang ,  Yunliang Zhu ,  Dongmin Park ,  Jingcheng Zhuang

IPC: H03B19/00 ,  H03L7/197 ,  H03L7/099 ,  H03K5/00

Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

公开(公告)号：US11025260B1

公开(公告)日：2021-06-01

申请号：US17003923

申请日：2020-08-26

Applicant: Qualcomm Incorporated

Inventor： Yue Chao ,  Marco Zanuso ,  Rajagopalan Rangarajan ,  Yiwu Tang

IPC: H03L7/099 ,  H03L7/197 ,  H03L7/089 ,  H03L7/093

Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.

公开(公告)号：US09379749B2

公开(公告)日：2016-06-28

申请号：US14704573

申请日：2015-05-05

Applicant: QUALCOMM Incorporated

Inventor： Lai Kan Leung ,  Chiewcharn Narathong ,  Rajagopalan Rangarajan ,  Dongling Pan ,  Yiwu Tang ,  Aleksandar Miodrag Tasic

IPC: H04B1/04 ,  H04B15/06 ,  H04B1/10 ,  H04B1/00 ,  H04B1/525

CPC classification number: H04B1/1081 ,  H03B2202/044 ,  H03B2202/046 ,  H04B1/005 ,  H04B1/0475 ,  H04B1/0483 ,  H04B1/525 ,  H04B15/06 ,  H04B2001/0491

Abstract: Aspects of a wireless apparatus for configuring a plurality of VCOs are provided. The apparatus may be a UE. The UE receives a configuration for a plurality of carriers. Each carrier corresponds to a different LO frequency. In addition, the UE determines a VCO frequency for generating each LO frequency. Further, the UE assigns each determined VCO frequency to each of a plurality of VCO modules based on a distance between the VCO modules and each of the determined VCO frequencies. The plurality of VCO modules are of a set of VCO modules including at least three VCO modules.

Abstract translation: 提供了用于配置多个VCO的无线设备的方面。 该装置可以是UE。 UE接收多个载波的配置。 每个载波对应于不同的LO频率。 此外，UE确定用于产生每个LO频率的VCO频率。 此外，UE基于VCO模块之间的距离和所确定的VCO频率中的每一个来将每个确定的VCO频率分配给多个VCO模块中的每一个。 多个VCO模块是包括至少三个VCO模块的一组VCO模块。

公开(公告)号：US08988158B2

公开(公告)日：2015-03-24

申请号：US13836932

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Sujiang Rong ,  Li Liu ,  Yiwu Tang

IPC: H03B5/12 ,  H03B5/02

CPC classification number: H03B5/1228 ,  H03B5/02 ,  H03B5/1215 ,  H03B5/1296 ,  H03B2200/0082 ,  H03B2200/009

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus provides a VCO signal. The apparatus is a VCO. The apparatus includes a first transconductance circuit. The apparatus further includes a second transconductance circuit coupled with the first transconductance circuit. The second transconductance circuit has a first configuration/mode (e.g., CMOS configuration/mode) and a second configuration/mode (e.g., NMOS configuration/mode or PMOS configuration/mode). The second transconductance circuit is configured to couple an input of the second transconductance circuit to the first transconductance circuit in the first configuration/mode. The second transconductance circuit is configured to isolate the input of the second transconductance circuit from the first transconductance circuit in the second configuration/mode. The second transconductance circuit may include a first transistor and a second transistor, and the input may be a gate of each of the first transistor and the second transistor.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置提供VCO信号。 该装置是VCO。 该装置包括第一跨导电路。 该装置还包括与第一跨导电路耦合的第二跨导电路。 第二跨导电路具有第一配置/模式（例如，CMOS配置/模式）和第二配置/模式（例如，NMOS配置/模式或PMOS配置/模式）。 第二跨导电路被配置为在第一配置/模式中将第二跨导电路的输入耦合到第一跨导电路。 第二跨导电路被配置为在第二配置/模式中将第二跨导电路的输入与第一跨导电路隔离。 第二跨导电路可以包括第一晶体管和第二晶体管，并且输入可以是第一晶体管和第二晶体管中的每一个的栅极。

公开(公告)号：US20140106681A1

公开(公告)日：2014-04-17

申请号：US13650844

申请日：2012-10-12

Applicant: QUALCOMM INCORPORATED

Inventor： Lai Kan Leung ,  Yiwu Tang ,  Chiewcharn Narathong

IPC: H04B1/62

CPC classification number: H04B1/62 ,  H04B1/30

Abstract: A wireless device includes: an antenna; and a polar-modulation transmitter coupled to the antenna and configured for two-point modulation, the transmitter including: a data input; a first signal path including a multiplier coupled to the data input and a voltage-controlled oscillator gain adaptation module coupled to the multiplier and configured to provide a gain value to the multiplier; and a second signal path coupled to the data input and including an analog phase-locked loop (PLL) including a voltage-controlled oscillator (VCO) coupled to the first signal path.

Abstract translation: 无线设备包括：天线; 以及耦合到所述天线并被配置用于两点调制的极性调制发射机，所述发射机包括：数据输入; 包括耦合到数据输入的乘法器的第一信号路径和耦合到乘法器并被配置为向乘法器提供增益值的压控振荡器增益适配模块; 以及耦合到所述数据输入并且包括模拟锁相环（PLL）的第二信号路径，所述模拟锁相环包括耦合到所述第一信号路径的压控振荡器（VCO）。

公开(公告)号：US20240413962A1

公开(公告)日：2024-12-12

申请号：US18333217

申请日：2023-06-12

Applicant: QUALCOMM Incorporated

Inventor： Dongmin Park ,  Dongling Pan ,  Yiwu Tang

IPC: H04L7/00 ,  H03K3/037 ,  H03K21/02

Abstract: This disclosure provides systems, methods, and devices for wireless communications that support configurable clock dividers for mixer operation in a radio frequency front end (RFFE). In a first aspect, an apparatus for wireless communications includes a first clock loop comprising a first plurality of latches generating a first plurality of clock signals with a corresponding first plurality of phases; and a second clock loop comprising a second plurality of latches generating a second plurality of clock signals with a corresponding second plurality of phases, wherein the first clock loop is configured to be enabled or disabled based on a first enable signal, and wherein the second clock loop is configured to be enabled or disabled based on a second enable signal. Other aspects and features are also claimed and described.

公开(公告)号：US11349483B1

公开(公告)日：2022-05-31

申请号：US17391406

申请日：2021-08-02

Applicant: QUALCOMM INCORPORATED

Inventor： Shilei Hao ,  Yunliang Zhu ,  Yiwu Tang ,  Dongmin Park

IPC: H03K23/00 ,  H03K23/44 ,  H03K3/356 ,  H03K21/10 ,  H03K23/40

Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

公开(公告)号：US20210091819A1

公开(公告)日：2021-03-25

申请号：US16578096

申请日：2019-09-20

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Yiwu Tang ,  Shrenik Patel

IPC: H04B1/403 ,  H04L5/14

Abstract: Wireless communication system may be configured to use different frequency bands for uplink communication and downlink communication. For example, a wireless system may use multiple frequency bands for downlink with carrier aggregation, and the wireless system may use only one frequency band for uplink. Up-conversion and down-conversion between baseband signals and RF signals, using a fixed frequency local oscillator signal may cause energy leak to an adjacent frequency band during transmission of signal and may result in interferences to other radio communication devices using the adjacent bands. To limit the amount of energy that leaks out of its assigned radio frequency bands, the UE may use local oscillator signals with different frequencies for up-conversion and down-conversion and may switch the frequencies of the local oscillator signals between reception of downlink signals and transmission of uplink signals.

公开(公告)号：US10903823B2

公开(公告)日：2021-01-26

申请号：US16147685

申请日：2018-09-29

Applicant: Qualcomm Incorporated

Inventor： Yiwu Tang ,  Sujiang Rong

IPC: H03K3/03 ,  H03B27/00 ,  H03B5/12 ,  H03K3/011

Abstract: An apparatus for radio-frequency (RF) oscillation signal production is disclosed. In example implementations, an apparatus includes an oscillator. The oscillator includes multiple oscillation stages that are coupled together in series into a ring. A respective oscillation stage of the multiple oscillation stages includes a transconductance amplifier and a core oscillator. The transconductance amplifier is coupled to a preceding oscillation stage. The core oscillator is coupled to the transconductance amplifier and to a succeeding oscillation stage, with the core oscillator including at least one output node configured to provide a respective output signal. In some implementations, at least one capacitor is coupled across at least the transconductance amplifier. In some aspects, at least one transistor of the transconductance amplifier is implemented with a silicon-on-insulator metal-oxide-semiconductor (SOI MOS) device that includes at least one back-gate terminal.

公开(公告)号：US10177772B2

公开(公告)日：2019-01-08

申请号：US15272307

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Jingcheng Zhuang ,  Xinhua Chen ,  Frederic Bossu ,  Yiwu Tang

IPC: H03L7/087 ,  H03L7/099 ,  H03L7/197 ,  H04L7/033 ,  H03L7/089 ,  H03L7/191

Abstract: A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.