Drill bit arcuate-shaped inserts with cutting edges and method of manufacture
    11.
    发明授权
    Drill bit arcuate-shaped inserts with cutting edges and method of manufacture 失效
    钻头圆弧形刀片和切削刃和制造方法

    公开(公告)号:US07331410B2

    公开(公告)日:2008-02-19

    申请号:US10923653

    申请日:2004-08-20

    CPC classification number: E21B10/50 E21B10/16

    Abstract: Disclosed are a variety of arcuate-shaped inserts for drill bits, and in particular, for placement in rolling cone cutters of drill bits. The arcuate inserts include 360° or ring-shaped inserts, as well as inserts of smaller arcuate length. The arcuate inserts are suitable for use in all surfaces of the rolling cone cutter, and in other locations in drill bits, and may have specialized cutting surfaces and material enhancements to enhance their cutting duty performance. Certain arcuate inserts may include stress relieving discontinuities such that, upon assembly into the cone or during drilling, the arcuate inserts may fragment in a controlled and predicted manner into shorter arcuate lengths.

    Abstract translation: 公开了用于钻头的各种弧形插入件,特别地,用于放置在钻头的滚动锥形切割器中。 弧形刀片包括360°或环形刀片,以及较小弓形长度的刀片。 弧形插入件适用于滚动圆锥切割机的所有表面,以及钻头中的其他位置,并且可具有专门的切割表面和材料增强功能,以增强其切割性能。 某些弓形刀片可包括应力消除不连续性,使得在组装到锥体中或在钻孔期间,弓形刀片可以以受控和预测的方式分段成较短的弓形长度。

    Assay system for simultaneous detection and measurement of multiple modified cellular proteins

    公开(公告)号:US20060166298A1

    公开(公告)日:2006-07-27

    申请号:US11392061

    申请日:2006-03-28

    CPC classification number: G01N33/6842 G01N33/6803 G01N33/6854 Y10S435/973

    Abstract: A method and kit for simultaneous detection and/or determination of a plurality of modified proteins in a sample. The method comprises: a) contacting the sample under mild protein denaturation conditions with a plurality of first antibodies capable of binding to a specific target protein, the first antibodies being immobilized on solid support material, each first antibody being differentiable from others by a differentiation parameter, whereby the first antibodies bind to respective target proteins present in the sample; b) removing unbound materials from the locus of the first antibodies; c) contacting the materials from step (b) with one or more second antibodies, each of which is specific to a class or subclass of modified proteins or with a plurality of second antibodies, each of which is specific to a modified protein, so as to bind the second antibody or antibodies to modified proteins in the sample; and d) detecting and/or determining a plurality of modified proteins in the sample. The kit comprises a plurality of primary antibodies immobilized on the above-mentioned solid support material, one or more buffers for lysing and for washing cellular material samples to be assayed, an assay buffer for conducting the assay, the buffer containing a sulfate or sulfonate detergent, and one or more second antibodies specific to the modified proteins. Also disclosed is a process for mild denaturation of modified proteins for use in such a procedure.

    Method and apparatus for a dummy SRAM cell
    13.
    发明授权
    Method and apparatus for a dummy SRAM cell 有权
    用于虚拟SRAM单元的方法和装置

    公开(公告)号:US07376032B2

    公开(公告)日:2008-05-20

    申请号:US11421497

    申请日:2006-06-01

    CPC classification number: G11C7/14 G11C7/12 G11C7/227 G11C11/412 G11C11/419

    Abstract: A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same first and second subsets of transistors, with the first transistors configured as a dummy bit line output circuit having substantially the same electrical characteristics as the first bit line output circuit of the standard SRAM cell. Further, the second transistors, which are not otherwise needed for the dummy SRAM cell function, are reconfigured as a voltage tie circuit for the dummy bit line output. Using the second transistors for this purpose obviates the need to add additional transistors to form a voltage tie circuit for configuring the dummy bit line output circuit as a load or driver for the dummy bit line.

    Abstract translation: 用于虚拟位线电路的虚拟SRAM单元使用与标准SRAM单元中使用的相同的晶体管,其包括配置为第一和第二位线输出电路的晶体管的第一和第二子集。 虚拟SRAM单元包括相同的第一和第二晶体管子集,其中第一晶体管配置为具有与标准SRAM单元的第一位线输出电路基本相同的电特性的虚拟位线输出电路。 此外,虚拟SRAM单元功能不另外需要的第二晶体管被重新配置为虚拟位线输出的电压连接电路。 为此,使用第二晶体管避免了增加额外的晶体管以形成用于将虚拟位线输出电路配置为虚拟位线的负载或驱动器的电压连接电路的需要。

    Hydro-lifter rock bit with PDC inserts

    公开(公告)号:US20060213692A1

    公开(公告)日:2006-09-28

    申请号:US11442520

    申请日:2006-05-26

    CPC classification number: E21B10/52 E21B10/16 E21B10/18 E21B17/1092

    Abstract: A novel rolling cone rock bit includes a plurality of PDC or other cutters mounted to the leg of the drill bit and positioned to cut the troublesome corner of the bottomhole. The plurality of cutters may be the primary cutting component at gage diameter, or may be redundant to gage teeth on a rolling cutter that cut to gage diameter. Consequently, the occurrence of undergage drilling from the wear and failure of the gage row on a rolling cutter is lessened. Another inventive feature is the inclusion of a mud ramp that creates a large junk slot from the borehole bottom up the drill bit. The resulting pumping action of the drill bit ramp speeds up the removal of chips or drilling cuttings from the bottom of the borehole, reduces the level of hydrostatic pressure at the bottom of the borehole and minimizes the wearing effect of cone inserts regrinding damaging drill cuttings.

    RNAi-based sensors, caged interfering RNAs, and methods of use thereof
    16.
    发明申请
    RNAi-based sensors, caged interfering RNAs, and methods of use thereof 审中-公开
    基于RNAi的传感器,笼式干扰RNA及其使用方法

    公开(公告)号:US20050059028A1

    公开(公告)日:2005-03-17

    申请号:US10716393

    申请日:2003-11-17

    Abstract: Methods of using labeled interfering RNAs to detect and/or quantitate target mRNAs in cells are provided. Related compositions, systems, and kits are also provided. Caged interfering RNAs (e.g., photoactivatable interfering RNAs), methods of using such caged RNAs, and related systems and kits are also provided. Methods and compositions for introducing interfering RNAs into cells, using RNAs covalently associated with protein transduction domains and/or lipids, are provided. Also provided are methods and compositions for selectively attenuating expression of a target mRNA by controlling expression of an interfering RNA.

    Abstract translation: 提供了使用标记的干扰RNA来检测和/或定量细胞中靶mRNA的方法。 还提供了相关的组合物,系统和试剂盒。 还提供了笼式干扰RNA(例如可光活化干扰RNA),使用这种笼式RNA的方法以及相关系统和试剂盒。 提供了使用与蛋白质转导结构域和/或脂质共价缔合的RNA将干扰RNA引入细胞的方法和组合物。 还提供了通过控制干扰RNA的表达来选择性地减弱靶mRNA表达的方法和组合物。

    Method and apparatus for reducing the number of rename registers in a
processor supporting out-of-order execution
    17.
    发明授权
    Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution 失效
    用于减少支持无序执行的处理器中的重命名寄存器的数量的方法和装置

    公开(公告)号:US5974524A

    公开(公告)日:1999-10-26

    申请号:US959647

    申请日:1997-10-28

    CPC classification number: G06F9/384 G06F9/3857 G06F9/3863

    Abstract: According to one aspect of the invention, a method is provided for maintaining the state of a processor having a plurality of physical registers and a rename register map which stores rename pairs that associate architected and physical registers, the rename register map having a plurality of entries which are associated with the physical registers, individual entries having an architected register field, an architected status bit and a history status bit. In one version, the method includes the steps of dispatching an instruction which targets an architected register; determining a presently architected entry in the rename register map in which an architected pointer in the architected register field of the entry matches the architected register pointer of the architected register targeted by the dispatched instruction and the architected status bit is set; resetting the architected status bit; setting the history status bit in the entry and saving the physical register pointer to a checkpoint recovery table if the dispatched instruction is interruptible or if the architected register of the dispatched instruction has not been targeted since the latest dispatched interruptible instruction; determining a next available rename register map entry; writing a pointer to the architected register targeted by the instruction into the architected register field and setting the architected status bit in the next available rename register map entry.

    Abstract translation: 根据本发明的一个方面,提供了一种用于维护具有多个物理寄存器的处理器的状态和存储重新命名对的重命名寄存器映射的方法,所述重命名对将结构化和物理寄存器相关联,重命名寄存器映射具有多个条目 其与物理寄存器相关联,具有架构化寄存器字段的单个条目,架构状态位和历史状态位。 在一个版本中,该方法包括调度针对架构化寄存器的指令的步骤; 确定重命名寄存器映射中的目前架构的条目,其中该条目的架构化寄存器字段中的架构指针与被调度指令所针对的架构化寄存器的架构化寄存器指针相匹配并且构建状态位被设置; 重置架构状态位; 如果发送的指令是可中断的,或者如果从最近发出的可中断指令起未指定调度指令的架构寄存器,则将条目的历史状态位设置为条目,并将物理寄存器指针保存到检查点恢复表; 确定下一个可用的重命名寄存器映射条目; 将指针写入到由架构寄存器字段指定的架构寄存器的指针,并将下一个可用重命名寄存器映射条目中的架构状态位置1。

    Adaptive read wordline voltage boosting apparatus and method for multi-port SRAM
    18.
    发明授权
    Adaptive read wordline voltage boosting apparatus and method for multi-port SRAM 有权
    用于多端口SRAM的自适应读取字线升压装置和方法

    公开(公告)号:US08659972B2

    公开(公告)日:2014-02-25

    申请号:US13543916

    申请日:2012-07-09

    CPC classification number: G11C11/419 G11C8/08 G11C11/418

    Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

    Abstract translation: 本发明的实施例涉及用于在需要时响应于过程电压 - 温度变化自适应地将SRAM的电源电压升高到SRAM(静态随机存取存储器)的系统和方法。 实施例包括模拟SRAM中的典型存储单元和读出电路的关键路径。 将触发信号施加到关键路径的字线输入端口,并将关键路径的输出与参考锁存信号进行比较,提供何时升压到SRAM的读出电路的电源电压的指示 。

    Adaptive Read Wordline Voltage Boosting Apparatus and Method for Multi-Port SRAM
    19.
    发明申请
    Adaptive Read Wordline Voltage Boosting Apparatus and Method for Multi-Port SRAM 有权
    用于多端口SRAM的自适应读取字线电压升压装置和方法

    公开(公告)号:US20130064031A1

    公开(公告)日:2013-03-14

    申请号:US13543916

    申请日:2012-07-09

    CPC classification number: G11C11/419 G11C8/08 G11C11/418

    Abstract: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

    Abstract translation: 本发明的实施例涉及用于在需要时响应于过程电压 - 温度变化自适应地将SRAM的电源电压升高到SRAM(静态随机存取存储器)的系统和方法。 实施例包括模拟SRAM中的典型存储单元和读出电路的关键路径。 将触发信号施加到关键路径的字线输入端口,并将关键路径的输出与参考锁存信号进行比较,提供何时升压到SRAM的读出电路的电源电压的指示 。

    Uncaging devices
    20.
    发明申请
    Uncaging devices 有权
    取消启动设备

    公开(公告)号:US20080030713A1

    公开(公告)日:2008-02-07

    申请号:US11893012

    申请日:2007-08-13

    CPC classification number: G01N21/6452

    Abstract: Uncaging devices that can be used to uncage photoactivatable caged components are provided. Consistent, uniform and/or high throughput processing of reactions and assays that include caged components is provided. Masked multiwell plates that can be used for uncaging photoactivatable caged components are provided. Methods and apparatus for initiating assays involving caged components are provided.

    Abstract translation: 提供了可用于解除可光灭活的笼式组件的非屏蔽设备。 提供了包括笼式组件的反应和测定的一致,均匀和/或高通量处理。 提供可用于解码可光致灭活笼式组件的蒙版多孔板。 提供了用于启动包含笼式组件的测定的方法和装置。

Patent Agency Ranking