公开(公告)号：US12152936B2

公开(公告)日：2024-11-26

申请号：US18331035

申请日：2023-06-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Todd Rearick ,  Thomas Raymond Thurston

IPC: G01J1/44 ,  B01J19/00 ,  H01L27/146 ,  H01L27/148

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

公开(公告)号：US12092579B2

公开(公告)日：2024-09-17

申请号：US18093213

申请日：2023-01-04

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

CPC classification number: G01N21/6456 ,  G01N21/6408 ,  G01N21/6454 ,  G05F1/46 ,  H01L27/14603 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14643 ,  G01N2021/6439

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US11869917B2

公开(公告)日：2024-01-09

申请号：US17149574

申请日：2021-01-14

Applicant: Quantum-Si Incorporated

Inventor： Eric A. G. Webster ,  Changhoon Choi ,  Dajiang Yang ,  Xin Wang ,  Todd Rearick ,  Kyle Preston ,  Ali Kabiri ,  Gerard Schmid

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14683

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, a charge storage region and the drain region may be positioned on a same side of the photodetection region. In some embodiments, at least one drain layer may be configured to receive incident photons and/or charge carriers via the photodetection region. In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in the plurality of pixels.

公开(公告)号：US11804499B2

公开(公告)日：2023-10-31

申请号：US16913688

申请日：2020-06-26

Applicant: Quantum-Si Incorporated

Inventor： Dajiang Yang ,  Farshid Ghasemi ,  Keith G. Fife ,  Todd Rearick ,  Ali Kabiri ,  Gerard Schmid ,  Eric A. G. Webster

IPC: H01L27/146 ,  H04N25/771

CPC classification number: H01L27/14609 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14636 ,  H04N25/771

Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.