公开(公告)号：US20240003811A1

公开(公告)日：2024-01-04

申请号：US18335458

申请日：2023-06-15

Applicant: Quantum-Si Incorporated

Inventor： Gerard Schmid ,  Dajiang Yang ,  Eric A.G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston ,  Brian Reed

IPC: G01N21/64 ,  H01L27/146

CPC classification number: G01N21/6454 ,  G01N21/6428 ,  H01L27/14603 ,  G01N21/6408 ,  G01N2021/6463

Abstract: Some aspects relate to an integrated circuit, comprising at least one photodetection region configured to generate charge carriers responsive to incident photons emitted from a sample, at least one charge storage region configured to receive the charge carriers from the photodetection region, and at least one controller configured to obtain information about the incident photons, the information comprising at least one member selected from the group comprising pulse duration and interpulse duration and at least one member selected from the group comprising wavelength information, luminescence lifetime information, and intensity information. In some embodiments, the information comprises at least three, four, and/or five members selected from the group comprising wavelength information, luminescence lifetime information, intensity information, pulse duration information, and interpulse duration information. In some embodiments, the information obtained may be used to identify the sample.

公开(公告)号：US20220328542A1

公开(公告)日：2022-10-13

申请号：US17716132

申请日：2022-04-08

Applicant: Quantum-Si Incorporated

Inventor： Xin Wang ,  Eric A.G. Webster ,  Todd Rearick

IPC: H01L27/146 ,  H04N5/369

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel, wherein the first pixel is proximate the second pixel in a mirrored configuration. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel that is proximate to the first pixel along a row direction, and a conductive line extending along a column direction that intersects with the row direction, wherein the conductive line is in electrical communication with a first component of the first pixel and a second component of the second pixel.

公开(公告)号：US20220186305A1

公开(公告)日：2022-06-16

申请号：US17548408

申请日：2021-12-10

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster

IPC: C12Q1/6869 ,  H01S3/11 ,  G01N21/64

Abstract: The present disclosure provides techniques for improving the rate and efficiency of charge transfer within an integrated circuit configured to receive incident photons. Some aspects of the present disclosure relate to integrated circuits that are configured to induce one or more intrinsic electric fields that increase the rate and efficiency of charge transfer within the integrated circuits. Some aspects of the present disclosure relate to integrated circuits configured to induce a charge carrier depletion in the photodetection region(s) of the integrated circuits. In some embodiments, the charge carrier depletion in the photodetection region(s) may be intrinsic, in that the depletion is induced even in the absence of external electric fields applied to the integrated circuit. Some aspects of the present disclosure relate to processes for operating and/or manufacturing integrated devices as described herein.

公开(公告)号：US20210318238A1

公开(公告)日：2021-10-14

申请号：US17224925

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

公开(公告)号：US20240353326A1

公开(公告)日：2024-10-24

申请号：US18539068

申请日：2023-12-13

Applicant: Quantum-Si Incorporated

Inventor： Gerard Schmid ,  Dajiang Yang ,  Eric A.G. Webster ,  Xin Wang ,  Todd Rearick ,  Changhoon Choi ,  Ali Kabiri ,  Kyle Preston

IPC: G01N21/64

CPC classification number: G01N21/6428 ,  G01N2021/6417 ,  G01N2021/6439

Abstract: Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

公开(公告)号：US20230253421A1

公开(公告)日：2023-08-10

申请号：US18133489

申请日：2023-04-11

Applicant: Quantum-Si Incorporated

Inventor： Dajiang Yang ,  Farshid Ghasemi ,  Keith G. Fife ,  Todd Rearick ,  Ali Kabiri ,  Gerard Schmidt ,  Eric A.G. Webster

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14623 ,  H04N25/771

Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

公开(公告)号：US20220392932A1

公开(公告)日：2022-12-08

申请号：US17831394

申请日：2022-06-02

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster

IPC: H01L27/146

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a plurality of photodetection regions and one or more intermediate regions between the photodetection regions. In some embodiments, the intermediate regions may comprise bulk semiconductor material that facilitates a transfer of noise charge carriers from the intermediate regions to drain regions associated with each photodetection region. In some embodiments, a drain device may be configured with a gate controlling the flow of charge carriers from the intermediate regions and photodetection regions to drain regions. In some embodiments, an integrated circuit may comprise an array of pixels and a control circuit configured to control a transfer of charge carriers in the array of pixels.

公开(公告)号：US20220128403A1

公开(公告)日：2022-04-28

申请号：US17507596

申请日：2021-10-21

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Todd Rearick ,  Tom Thurston

IPC: G01J1/44 ,  H01L27/148 ,  H01L27/146 ,  B01J19/00

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

公开(公告)号：US20220128402A1

公开(公告)日：2022-04-28

申请号：US17507585

申请日：2021-10-21

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Todd Rearick ,  Tom Thurston

IPC: G01J1/44 ,  H01L27/148 ,  B01J19/00

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

公开(公告)号：US20210318242A1

公开(公告)日：2021-10-14

申请号：US17224899

申请日：2021-04-07

Applicant: Quantum-Si Incorporated

Inventor： Eric A.G. Webster ,  Dajiang Yang ,  Xin Wang ,  Zhaoyu He ,  Changhoon Choi ,  Peter J. Lim ,  Todd Rearick

IPC: G01N21/64 ,  G05F1/46 ,  H01L27/146

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.