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    INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR
    11.
    发明申请
    INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR 有权
    具有包括注射锁定振荡器的时钟电路的集成电路

    公开(公告)号：US20140333386A1

    公开(公告)日：2014-11-13

    申请号：US14444669

    申请日：2014-07-28

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Brian S. Leibowitz

    IPC: H03L7/099

    CPC classification number: H03L7/24 ,  H03K5/26 ,  H03K2005/00286 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995

    Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

    Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。

    Binary Pixel Circuit Architecture
    12.
    发明申请
    Binary Pixel Circuit Architecture 有权
    二进制像素电路架构

    公开(公告)号：US20140054446A1

    公开(公告)日：2014-02-27

    申请号：US13961842

    申请日：2013-08-07

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic

    IPC: H01L27/146

    CPC classification number: H01L27/14609 ,  H04N5/3355 ,  H04N5/37455

    Abstract: An integrated-circuit image sensor that includes an array of pixel regions composed of binary pixel circuits. Each binary pixel circuit includes a binary amplifier having an input and an output. The binary amplifier generates a binary signal at the output in response to whether an input voltage at the input exceeds a switching threshold voltage level of the binary amplifier. A light-detecting element of the binary pixel circuit is coupled to the input of the binary amplifier. Initialization circuitry of the binary pixel circuit is coupled to the input of the binary amplifier. The initialization circuitry sets the input voltage to a level that is offset relative to the switching threshold voltage level of the binary amplifier by an offset voltage amount, the offset voltage amount representing a threshold amount of light incident on the light detecting element.

    Abstract translation: 一种集成电路图像传感器，包括由二进制像素电路组成的像素区域阵列。 每个二进制像素电路包括具有输入和输出的二进制放大器。 二进制放大器响应于输入端的输入电压是否超过二进制放大器的开关阈值电压电平，在输出端产生二进制信号。 二进制像素电路的光检测元件耦合到二进制放大器的输入端。 二进制像素电路的初始化电路耦合到二进制放大器的输入端。 初始化电路将输入电压设置为相对于二进制放大器的开关阈值电压电平偏移偏移电压量的电平，偏移电压量表示入射在光检测元件上的阈值光量。

    Phase calibration of clock signals
    13.
    发明授权
    Phase calibration of clock signals 有权

    公开(公告)号：US10367636B2

    公开(公告)日：2019-07-30

    申请号：US16156868

    申请日：2018-10-10

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H03L7/081 ,  H04L7/00 ,  H04L25/03 ,  H04L25/02

    Abstract: A receiver with clock phase calibration is disclosed. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR
    16.
    发明申请
    INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR 有权

    公开(公告)号：US20160226496A1

    公开(公告)日：2016-08-04

    申请号：US15009485

    申请日：2016-01-28

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Brian S. Leibowitz

    IPC: H03L1/00 ,  H03L7/24

    CPC classification number: H03L1/00 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/24

    Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

    PHASE CALIBRATION OF CLOCK SIGNALS
    17.
    发明申请
    PHASE CALIBRATION OF CLOCK SIGNALS 审中-公开

    公开(公告)号：US20190173661A1

    公开(公告)日：2019-06-06

    申请号：US16156868

    申请日：2018-10-10

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H03L7/081 ,  H04L25/03 ,  H04L7/00

    CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/0337 ,  H04L25/0292 ,  H04L25/03 ,  H04L25/03057 ,  H04L2025/03802

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    Image sensor sampled at non-uniform intervals
    19.
    发明授权
    Image sensor sampled at non-uniform intervals 有权
    图像传感器以不均匀的间隔进行采样

    公开(公告)号：US09521338B2

    公开(公告)日：2016-12-13

    申请号：US14355814

    申请日：2012-11-08

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  David Geoffrey Stork ,  Jie Shen ,  Yeuyong Wang ,  Marko Aleksic

    IPC: H04N5/353 ,  H04N5/335 ,  H04N5/3745 ,  H04N5/369

    CPC classification number: H04N5/353 ,  H04N5/3355 ,  H04N5/3696 ,  H04N5/37455 ,  H04N5/37457

    Abstract: In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.

    Abstract translation: 在集成电路图像传感器中，在连续的采样间隔之后从像素阵列中读出二进制采样值，该采样间隔共同跨越图像曝光间隔并且包括至少两个不等长度的采样间隔。 根据该像素是否产生处于第一状态或第二状态的二进制样本，阵列的每个像素在每个连续采样间隔之后有条件地重置。

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