公开(公告)号：US11335571B2

公开(公告)日：2022-05-17

申请号：US16930106

申请日：2020-07-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki Tsuchiya ,  Akira Matsumoto

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.

公开(公告)号：US09722066B2

公开(公告)日：2017-08-01

申请号：US15055604

申请日：2016-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Tsuchiya ,  Hiroshi Kimura ,  Takashi Ide ,  Yorinobu Kunimune

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/20 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L23/528 ,  H01L23/53223 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To enhance electromigration resistance of an electrode.A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

公开(公告)号：US09559052B2

公开(公告)日：2017-01-31

申请号：US15047623

申请日：2016-02-18

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami ,  Yukio Miura ,  Hideaki Tsuchiya

IPC: H01L21/00 ,  H01L23/522 ,  H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/263 ,  H01L21/265 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L23/528 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.

Abstract translation: 半导体器件包括层间绝缘膜INS2，形成在层间绝缘膜INS2中的相邻的Cu布线M1W和与层间绝缘膜INS2的表面接触的绝缘阻挡膜BR1和Cu布线M1W和盖的表面 层间绝缘膜INS2和Cu布线M1W。 在相邻的Cu配线M1W之间，层间绝缘膜INS2在其表面具有损伤层DM1，并且在比损伤深的位置具有比损伤层DM1的氮浓度高的氮浓度的电场缓和层ER1 层DM1。

公开(公告)号：US20160181411A1

公开(公告)日：2016-06-23

申请号：US15055604

申请日：2016-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Tsuchiya ,  Hiroshi Kimura ,  Takashi Ide ,  Yorinobu Kunimune

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L23/528 ,  H01L23/53223 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To enhance electromigration resistance of an electrode.A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).

Abstract translation: 提高电极的电迁移率。 漏电极部分地形成在漏极焊盘的侧表面上。 在这种情况下，漏电极与漏极焊盘集成，并且在漏极焊盘的侧表面沿着第一方向（y方向）延伸。 凹部在平面图中位于与漏电极重叠的区域中。 漏电极的至少一部分被埋在凹部中。 面向排水垫的凹部的侧面在第一方向（y方向）上进入排水垫。

公开(公告)号：US09281276B2

公开(公告)日：2016-03-08

申请号：US14381572

申请日：2013-11-08

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami ,  Yukio Miura ,  Hideaki Tsuchiya

IPC: H01L21/00 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/263 ,  H01L21/265 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.

Abstract translation: 半导体器件包括层间绝缘膜INS2，形成在层间绝缘膜INS2中的相邻的Cu布线M1W和与层间绝缘膜INS2的表面接触的绝缘阻挡膜BR1和Cu布线M1W和盖的表面 层间绝缘膜INS2和Cu布线M1W。 在相邻的Cu配线M1W之间，层间绝缘膜INS2在其表面具有损伤层DM1，并且在比损伤深的位置具有比损伤层DM1的氮浓度高的氮浓度的电场缓和层ER1 层DM1。