公开(公告)号：US20160155726A1

公开(公告)日：2016-06-02

申请号：US15017666

申请日：2016-02-07

Applicant: Renesas Electronics Corporation

Inventor： Takamitsu Kanazawa ,  Satoru Akiyama

IPC: H01L25/07 ,  H01L23/31 ,  H01L23/538 ,  H01L29/78 ,  H01L23/00 ,  H01L29/808 ,  H01L29/16

CPC classification number: H01L25/072 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/3702 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40105 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/84

Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，形成在半导体芯片CHP1的前表面上的栅极焊盘GPj被布置成比其他引线（漏极引线DL和栅极引线GL）更靠近源极引线SL。 结果，根据本发明，可以缩短栅极焊盘GPj和源极引线SL之间的距离，从而可以缩短用于将栅极焊盘GPj和源极引线SL连接在一起的焊丝Wgj的长度。 因此，根据本发明，可以充分地减小存在于导线Wgj中的寄生电感。