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公开(公告)号：US20150169482A1
公开(公告)日：2015-06-18
申请号：US14575491
申请日：2014-12-18
Applicant: RF MICRO DEVICES, INC.
Inventor： Christopher Truong Ngo , Alexander Wayne Hietala , Christian Rye Iversen , Ruediger Bauder
IPC: G06F13/362 , G06F1/08
CPC classification number: G06F13/3625 , G06F13/4278 , Y02D10/14 , Y02D10/151
Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.
Abstract translation: 公开了一种总线接口系统，其包括通过总线耦合的主总线控制器和从总线控制器。 从总线控制器包括允许数据沿着总线传输的解码器。 解码器包括振荡器，第一计数器和比较电路。 振荡器被配置为通过由输入数据信号定义的数据脉冲使能，并在使能时产生振荡脉冲。 第一个对振荡脉冲进行计数，并指示在时隙期间产生的振荡脉冲的数量。 比较电路被配置为具有参考号的该号码，并且响应于该数量大于参考参数而生成表示第一逻辑值的数据输出，并且响应于小于参考的数字表示第二逻辑值 参数。
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公开(公告)号：US20140375390A1
公开(公告)日：2014-12-25
申请号：US14304149
申请日：2014-06-13
Applicant: RF Micro Devices, Inc.
Inventor： Derek Schooley , Alexander Wayne Hietala
CPC classification number: H03F3/21 , H03F1/0261 , H03F3/191 , H03F2200/18 , H03F2200/27 , H03F2200/451 , H03G3/30
Abstract: Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.
Abstract translation: 功率放大器电路包括功率放大器，其包括输入节点和输出节点，偏置电路，可选阻抗网络和输入电容器。 输入电容器耦合到功率放大器的输入节点。 偏置电路通过可选择的阻抗网络耦合到功率放大器的输入节点。 功率放大器可在低功率工作模式和高功率工作模式下工作。 在低功率操作模式中，偏置电路将第一偏置电流传送到功率放大器的输入节点，并且选择可选阻抗的第一阻抗级别。 在高功率操作模式中，偏置电路将第二偏置电流传递到功率放大器的输入节点，并且选择可选择阻抗的第二阻抗水平。
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公开(公告)号：US20140035673A1
公开(公告)日：2014-02-06
申请号：US13828647
申请日：2013-03-14
Applicant: RF MICRO DEVICES, INC.
Inventor： Jeffery Peter Ortiz , Alexander Wayne Hietala
IPC: H03F3/45
CPC classification number: H03F3/45076 , H03F1/0261 , H03F3/4508 , H03F2203/45244 , H03F2203/45294 , H03F2203/45394 , H03F2203/45481 , H03F2203/45542 , H03F2203/45621 , H03F2203/45731
Abstract: Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.
Abstract translation: 差分功率放大器电路包括差分晶体管对，输入变压器和偏置电路。 差分晶体管对中的每个晶体管的基极接触可通过耦合电容耦合到输入变压器。 耦合电容器可以被设计为在输入变压器周围以期望的频率范围谐振，从而将期望的信号传递到差分晶体管对，同时阻挡不期望的信号。 偏置电路可以包括一对射极跟随器晶体管，每个射极跟随器晶体管在发射极处耦合到差分晶体管对中的每个晶体管的基极接触，并且适于偏置差分晶体管对以最大化效率和稳定性。
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公开(公告)号：US20130135043A1
公开(公告)日：2013-05-30
申请号：US13689883
申请日：2012-11-30
Applicant: RF Micro Devices, Inc.
Inventor： Alexander Wayne Hietala , Jeffery Peter Ortiz , David Halchin , Jackie Johnson , Wendel Charles
IPC: H03F3/21
CPC classification number: H03F3/211 , H03F1/0277 , H03F3/195 , H03F3/245 , H03F3/72 , H03F2200/429 , H03F2200/507 , H03F2200/537 , H03F2203/21145 , H03F2203/7209 , H03F2203/7227
Abstract: Multimode radio frequency (RF) amplifier systems and techniques are disclosed. In one embodiment, a multimode radio frequency (RF) amplifier system has a first RF amplifier and a second RF amplifier. The first RF amplifier may support a first RF communication standard. The second RF amplifier may support a second RF communication standard. The first RF amplifier includes an auxiliary circuit. The auxiliary circuit may provide a service or a utility to a second RF amplifier. For example, the auxiliary circuit may generate a supply voltage to power the second RF amplifier.
Abstract translation: 公开了多模射频（RF）放大器系统和技术。 在一个实施例中，多模射频（RF）放大器系统具有第一RF放大器和第二RF放大器。 第一RF放大器可以支持第一RF通信标准。 第二RF放大器可以支持第二RF通信标准。 第一RF放大器包括辅助电路。 辅助电路可以向第二RF放大器提供服务或实用工具。 例如，辅助电路可以产生电源电压以对第二RF放大器供电。
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公开(公告)号：US20160087483A1
公开(公告)日：2016-03-24
申请号：US14851642
申请日：2015-09-11
Applicant: RF Micro Devices, Inc.
Inventor： Alexander Wayne Hietala , Nadim Khlat
Abstract: Antenna array calibration for wireless charging is disclosed. A wireless charging system is provided and configured to calibrate antenna elements in a wireless charging station based on a feedback signal provided by a wireless charging device. The antenna elements in the wireless charging station transmit wireless radio frequency (RF) charging signals to the wireless charging device. The wireless charging device provides the feedback signal to the wireless charging station to indicate total RF power in the wireless RF charging signals. The wireless charging station is configured to adjust transmitter phases associated with the antenna elements based on the feedback signal until the total RF power in the wireless RF charging signals is maximized. By calibrating the antenna elements based on the feedback signal, it is possible to achieve phase coherency among the antenna elements without requiring factory calibration.
Abstract translation: 公开了用于无线充电的天线阵列校准。 提供无线充电系统并配置为基于由无线充电装置提供的反馈信号来校准无线充电站中的天线元件。 无线充电站中的天线元件向无线充电装置发送无线射频（RF）充电信号。 无线充电装置向无线充电站提供反馈信号以指示无线RF充电信号中的总RF功率。 无线充电站被配置为基于反馈信号调整与天线元件相关联的发射机相位，直到无线RF充电信号中的总RF功率最大化为止。 通过基于反馈信号校准天线元件，可以在不需要工厂校准的情况下实现天线元件之间的相位一致性。
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Patent Agency Ranking
公开(公告)号：US20150193321A1
公开(公告)日：2015-07-09
申请号：US14659379
申请日：2015-03-16
Applicant: RF Micro Devices, Inc.
Inventor： Christopher Truong Ngo , Alexander Wayne Hietala
CPC classification number: G06F11/3027 , G06F1/10 , G06F1/26 , G06F11/1004 , G06F11/1052 , G06F11/1604 , G06F11/221
Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.
Abstract translation: 公开了总线接口系统的实施例及其操作方法。 在一个实施例中，总线接口系统包括主总线控制器和多个从总线控制器，每个从总线控制器耦合到总线。 主总线控制器被配置为沿着表示有效载荷段的总线产生第一组数据脉冲。 每个从总线控制器沿着表示有效载荷段的总线解码第一组数据脉冲，并执行错误检查。 然后，每个从总线控制器被配置为沿着总线生成确认脉冲，以指示从总线控制器的特定错误检查已经通过。 以这种方式，总线接口系统可以执行组写总线功能，并且主总线控制器可以确定多个从总线控制器各自接收到有效载荷段的准确副本。
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公开(公告)号：US20150193297A1
公开(公告)日：2015-07-09
申请号：US14659328
申请日：2015-03-16
Applicant: RF Micro Devices, Inc.
Inventor： Christopher Truong Ngo , Alexander Wayne Hietala
CPC classification number: G06F11/3027 , G06F1/10 , G06F1/26 , G06F11/00 , G06F11/0745 , G06F11/221 , G06F13/3625 , H04L1/00 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/1692 , H04L7/0276 , H04L2001/0094
Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.
Abstract translation: 公开了总线接口系统的实施例。 总线接口系统包括主总线控制器和耦合到总线的从总线控制器。 主总线控制器和从总线控制器配置为使用错误代码和错误检查执行读操作。 例如，错误代码可以是循环冗余码（CRC）。 以这种方式，在从总线控制器和主总线控制器之间的通信期间确保精度。
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公开(公告)号：US09041466B2
公开(公告)日：2015-05-26
申请号：US13828647
申请日：2013-03-14
Applicant: RF Micro Devices, Inc.
Inventor： Jeffery Peter Ortiz , Alexander Wayne Hietala
CPC classification number: H03F3/45076 , H03F1/0261 , H03F3/4508 , H03F2203/45244 , H03F2203/45294 , H03F2203/45394 , H03F2203/45481 , H03F2203/45542 , H03F2203/45621 , H03F2203/45731
Abstract: Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.
Abstract translation: 差分功率放大器电路包括差分晶体管对，输入变压器和偏置电路。 差分晶体管对中的每个晶体管的基极接触可通过耦合电容耦合到输入变压器。 耦合电容器可以被设计为在输入变压器周围以期望的频率范围谐振，从而将期望的信号传递到差分晶体管对，同时阻止不期望的信号。 偏置电路可以包括一对射极跟随器晶体管，每个射极跟随器晶体管在发射极处耦合到差分晶体管对中的每个晶体管的基极接触，并且适于偏置差分晶体管对以最大化效率和稳定性。
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公开(公告)号：US20150002220A1
公开(公告)日：2015-01-01
申请号：US14487352
申请日：2014-09-16
Applicant: RF Micro Devices, Inc.
Inventor： Alexander Wayne Hietala , Timothy E. Daughters
CPC classification number: H03F1/0233 , H03F1/0222 , H03F1/32 , H03F3/19 , H03F3/24 , H03F3/245 , H03F2200/451 , H03F2200/465
Abstract: The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector.
Abstract translation: 示例性实施例包括基于非线性功率检测器输出和相关联的功率放大器输出电平的测量以及一组数据点的方法，计算机可读介质和用于校准射频设备的非线性功率检测器的设备 其特征在于标称非线性功率检测器。 表征标称非线性功率检测器的数据点集合作为标称功率检测器输出数据存储在校准系统存储器中。 测量的非线性功率检测器输出，功率放大器输出电平和额定功率检测器输出数据用于确定功率检测器误差函数，其表征非线性功率检测器的响应与标称非线性 功率检测器 功率检测器误差函数和标称功率检测器输出数据用于开发存储在非线性功率检测器中的校准功率检测器输出数据组。
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公开(公告)号：US20130113556A1
公开(公告)日：2013-05-09
申请号：US13668641
申请日：2012-11-05
Applicant: RF Micro Devices, Inc.
Inventor： Jeffery P. Ortiz , Alexander Wayne Hietala
IPC: H03G3/20
CPC classification number: H03G3/3042
Abstract: In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system.
Abstract translation: 在一个实施例中，通过将第一控制节点处的控制电压与缩放的电池电压进行比较来限制功率放大器的控制系统的饱和度，然后当控制电压超过定标的电池时，从第一控制节点引出误差电流 电池电压。 第一控制节点可以位于反馈控制系统中的跨导放大器之后。
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