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    Serial bus buffer with noise reduction
    1.
    发明授权
    Serial bus buffer with noise reduction 有权
    具有降噪功能的串行总线缓冲器

    公开(公告)号：US09519612B2

    公开(公告)日：2016-12-13

    申请号：US14160900

    申请日：2014-01-22

    Applicant: RF Micro Devices, Inc.

    Inventor： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Eric K. Bolton

    IPC: G06F13/24 ,  G06F13/42

    CPC classification number: G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

    Abstract translation: 公开了一种具有串行总线缓冲器的数字通信控制系统，该串行总线缓冲器包括适于支持通过主总线的串行通信的主接口，适于支持通过缓冲总线的串行通信的缓冲接口以及耦合在主总线与 缓冲总线。 主总线耦合到第一设备和至少一个第二设备，并且缓冲总线耦合到至少一个第三设备。 控制器适于在主接口处接收第一数据信号和时钟信号，并在缓冲接口处复制第一数据信号和时钟信号。

    AUTO-CONFIGURATION OF DEVICES BASED UPON CONFIGURATION OF SERIAL INPUT PINS AND SUPPLY
    2.
    发明申请
    AUTO-CONFIGURATION OF DEVICES BASED UPON CONFIGURATION OF SERIAL INPUT PINS AND SUPPLY 有权
    基于串行输入引脚和电源配置的器件自动配置

    公开(公告)号：US20150106541A1

    公开(公告)日：2015-04-16

    申请号：US14511602

    申请日：2014-10-10

    Applicant: RF Micro Devices, Inc.

    Inventor： William David Southcombe ,  Christopher Truong Ngo ,  Joseph Hubert Colles

    IPC: G06F13/42

    CPC classification number: G06F13/4221 ,  G06F13/4282

    Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

    Abstract translation: 设备包括存储器，至少两个输入/输出（IO）引脚和从标识符（ID）选择电路。 存储器存储从属ID，其在串行通信过程中将设备标识到其他设备。 从机ID选择电路根据哪个IO引脚耦合到电源电压来改变存储的从机ID。 通过根据哪个IO引脚耦合到电源电压来改变器件的从器件ID，具有其他相同的从器件ID的多个器件可以改变其从器件ID，以便参与同一总线上的串行通信处理 。 此外，可以改变设备的从设备ID，而不需要在设备上使用附加的IO引脚。

    Start of sequence detection for one wire bus
    4.
    发明授权
    Start of sequence detection for one wire bus 有权

    公开(公告)号：US10579580B2

    公开(公告)日：2020-03-03

    申请号：US14659292

    申请日：2015-03-16

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

    IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F13/362

    Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

    Group write technique for a bus interface system
    6.
    发明授权
    Group write technique for a bus interface system 有权

    公开(公告)号：US10049026B2

    公开(公告)日：2018-08-14

    申请号：US14659379

    申请日：2015-03-16

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

    IPC: G06F11/30 ,  G06F1/26 ,  G06F1/10 ,  G06F11/22 ,  G06F11/16 ,  G06F11/10

    Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

    Auto-configuration of devices based upon configuration of serial input pins and supply
    7.
    发明授权
    Auto-configuration of devices based upon configuration of serial input pins and supply 有权

    公开(公告)号：US09720872B2

    公开(公告)日：2017-08-01

    申请号：US14511602

    申请日：2014-10-10

    Applicant: RF Micro Devices, Inc.

    Inventor： William David Southcombe ,  Christopher Truong Ngo ,  Joseph Hubert Colles

    IPC: G06F13/42

    CPC classification number: G06F13/4221 ,  G06F13/4282

    Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

    Power management architecture for modulated and constant supply operation
    8.
    发明授权
    Power management architecture for modulated and constant supply operation 有权
    电源管理架构，用于调制和恒定供电操作

    公开(公告)号：US09246460B2

    公开(公告)日：2016-01-26

    申请号：US14072140

    申请日：2013-11-05

    Applicant: RF Micro Devices, Inc.

    Inventor： Nadim Khlat ,  Michael R. Kay ,  Phillippe Gorisse ,  Christopher Truong Ngo

    IPC: H03G3/00 ,  H03F3/04 ,  H03G3/30 ,  H02M3/07 ,  H02M3/158 ,  H03F1/02 ,  H03F3/24 ,  H03F3/45 ,  H02M1/00

    CPC classification number: H03G3/3042 ,  H02M3/07 ,  H02M3/158 ,  H02M2001/0032 ,  H03F1/0227 ,  H03F3/24 ,  H03F3/45663 ,  Y02B70/16

    Abstract: A power management system, which includes a parallel amplifier circuit and a switch mode power supply converter, is disclosed. The switch mode power supply converter cooperatively operates with the parallel amplifier circuit to form the power management system. The power management system operates in one of a high power modulation mode, a medium power modulation mode, and a low power average power tracking mode. Further, during the high power modulation mode and the medium power modulation mode, the power management system controls a power amplifier supply voltage to a radio frequency power amplifier to provide envelope tracking. During the low power average power tracking mode, the power management system controls the power amplifier supply voltage to the radio frequency power amplifier to provide average power tracking.

    Abstract translation: 公开了一种电源管理系统，其包括并联放大器电路和开关模式电源转换器。 开关模式电源转换器与并行放大器电路协同工作，形成电源管理系统。 电源管理系统以高功率调制模式，中等功率调制模式和低功率平均功率跟踪模式之一工作。 此外，在高功率调制模式和中等功率调制模式期间，电力管理系统控制向射频功率放大器的功率放大器电源电压以提供包络跟踪。 在低功率平均功率跟踪模式下，电源管理系统控制功率放大器对射频功率放大器的电源电压，以提供平均功率跟踪。

    WRITE TECHNIQUE FOR A BUS INTERFACE SYSTEM
    9.
    发明申请
    WRITE TECHNIQUE FOR A BUS INTERFACE SYSTEM 审中-公开
    用于总线接口系统的写入技术

    公开(公告)号：US20150193298A1

    公开(公告)日：2015-07-09

    申请号：US14659355

    申请日：2015-03-16

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

    IPC: G06F11/08 ,  G06F11/30 ,  G06F11/22

    Abstract: Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.

    Abstract translation: 公开了总线接口系统的实施例。 在一个实施例中，总线接口系统包括主总线控制器和耦合到总线的从总线控制器。 主总线控制器被配置为沿着表示有效载荷段的总线产生第一组数据脉冲。 从总线控制器被配置为将表示有效载荷段的第一组数据脉冲解码为经解码的有效载荷段。 从属总线控制器然后被配置为对解码的有效载荷段执行第一错误检查。 此外，从总线控制器被配置为沿着总线产生确认信号，使得确认信号指示经解码的有效载荷段通过第一错误检查。 以这种方式，主总线控制器可以确定从总线控制器接收到有效载荷段的准确副本。

    POWER MANAGEMENT SYSTEM FOR A BUS INTERFACE SYSTEM
    10.
    发明申请
    POWER MANAGEMENT SYSTEM FOR A BUS INTERFACE SYSTEM 审中-公开
    用于总线接口系统的电源管理系统

    公开(公告)号：US20150192974A1

    公开(公告)日：2015-07-09

    申请号：US14659371

    申请日：2015-03-16

    Applicant: RF Micro Devices, Inc.

    Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

    IPC: G06F1/26 ,  G06F13/40 ,  G06F13/364 ,  G06F1/32

    Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

    Abstract translation: 公开了总线接口系统的实施例。 在一个实施例中，总线接口系统包括总线控制器和沿总线耦合的从总线控制器。 主总线控制器被配置为产生由总线控制器沿总线接收的输入数据信号。 从总线控制器包括被配置为将来自主总线控制器的输入数据信号转换成电源电压的功率转换电路。 通过提供电源转换电路，从总线控制器使用输入数据信号供电，而不需要额外的总线来将电源电压传送到从总线控制器。

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