公开(公告)号：USD823270S1

公开(公告)日：2018-07-17

申请号：US29598520

申请日：2017-03-27

Applicant: ROHM CO., LTD.

Designer： Kentaro Nasu ,  Kenji Nishida

公开(公告)号：US12100764B2

公开(公告)日：2024-09-24

申请号：US17428555

申请日：2020-02-07

Applicant: ROHM CO., LTD.

Inventor： Kentaro Nasu ,  Yasuhiro Kondo ,  Takaaki Yoshioka

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7819

Abstract: A semiconductor device includes a semiconductor layer that has a main surface, a trench gate structure that includes a trench formed in the main surface and having a first sidewall at one side, a second sidewall at the other side and a bottom wall in a cross-sectional view, an insulation layer formed on an inner wall of the trench, and a gate electrode embedded in the trench with the insulation layer between the trench and the gate electrode and having an upper end portion positioned at a bottom-wall side with respect to the main surface, a plurality of first-conductivity-type drift regions that are respectively formed in a region at the first sidewall side of the trench and in a region at the second sidewall side of the trench such as to face each other with the trench interposed therebetween in a surface layer portion of the main surface and that are positioned in a region at the main surface side with respect to the bottom wall, and a plurality of first-conductivity-type source/drain regions that are formed in surface layer portions of the plurality of drift regions, respectively.

公开(公告)号：US11955544B2

公开(公告)日：2024-04-09

申请号：US17454433

申请日：2021-11-10

Applicant: ROHM CO., LTD.

Inventor： Kentaro Nasu

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/866

CPC classification number: H01L29/7808 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

公开(公告)号：US11830792B2

公开(公告)日：2023-11-28

申请号：US17290087

申请日：2019-11-14

Applicant: ROHM CO., LTD.

Inventor： Kentaro Nasu

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/49527 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/25 ,  H01L24/33 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/074 ,  H01L23/3135 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/244 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2224/29139 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/3315 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/92244 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15162

Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

公开(公告)号：US10985030B2

公开(公告)日：2021-04-20

申请号：US16684817

申请日：2019-11-15

Applicant: Rohm Co., Ltd.

Inventor： Kentaro Nasu ,  Kanako Deguchi

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L21/02 ,  H01L21/304

Abstract: A method for manufacturing a semiconductor device includes preparing a lead frame, mounting a semiconductor element on an obverse face of the lead frame, forming a sealing resin covering the semiconductor element, forming a groove on a reverse face of the lead frame, and removing a portion of the lead frame and a portion of the sealing resin along a disposal region that is narrower than the groove and entirely overlaps with the groove. The preparing of the lead frame includes forming at least one recess located in the disposal region and having an end that is open in the thickness direction. The forming of the groove includes exposing the recess on a side of the reverse face of the lead frame. The removing is performed with reference to the recess.

公开(公告)号：US10522674B2

公开(公告)日：2019-12-31

申请号：US15597469

申请日：2017-05-17

Applicant: ROHM CO., LTD.

Inventor： Kentaro Nasu

IPC: H01L29/16 ,  H01L29/78 ,  H01L27/02 ,  H01L29/417 ,  H01L29/423 ,  H01L29/866

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.