公开(公告)号：US08214777B2

公开(公告)日：2012-07-03

申请号：US12419377

申请日：2009-04-07

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G01R31/025 ,  G11C29/006 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2029/5602

摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

摘要翻译： 泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。 与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流， 类型设备已超过阈值。 测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

公开(公告)号：US07994042B2

公开(公告)日：2011-08-09

申请号：US11924735

申请日：2007-10-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/00

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US07968944B2

公开(公告)日：2011-06-28

申请号：US12541641

申请日：2009-08-14

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/12 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US07911025B2

公开(公告)日：2011-03-22

申请号：US12127080

申请日：2008-05-27

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。

公开(公告)号：US07873891B2

公开(公告)日：2011-01-18

申请号：US12114853

申请日：2008-05-05

申请人： Yuen H. Chan ,  Rajiv V. Joshi

发明人： Yuen H. Chan ,  Rajiv V. Joshi

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028

摘要： A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

摘要翻译： 可以在测试电路中使用的测试电路和可编程分压器。 可编程分压器产生可以数字选择的电压差信号。 测试电路可用于测试和表征读出放大器。 可编程分压器产生具有所选极性和幅度的信号，该极性和幅度被提供给被测试的读出放大器。 读出放大器设置并输出锁存。 根据预期值检查锁存内容。 可以改变差值电压，重新测试路径以找到通过点和故障点。

公开(公告)号：US07774660B2

公开(公告)日：2010-08-10

申请号：US12131307

申请日：2008-06-02

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

公开(公告)号：US07751267B2

公开(公告)日：2010-07-06

申请号：US11782071

申请日：2007-07-24

申请人： Rajiv V. Joshi ,  Rouwaida Kanj ,  Jayakumaran Sivagnaname

发明人： Rajiv V. Joshi ,  Rouwaida Kanj ,  Jayakumaran Sivagnaname

IPC分类号： G11C7/12 ,  G11C11/41 ,  G11C11/413

CPC分类号： G11C7/12 ,  G11C11/412

摘要： A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in accordance with a memory operation. Control logic is configured to enable at least one of the plurality of transistors to provide a programmable precharge voltage to the node in accordance with a respective threshold voltage drop from the supply voltage of one of the plurality of transistors.

摘要翻译： 可编程预充电电路包括多个晶体管。 每个晶体管具有与多个晶体管中的其它晶体管不同的阈值电压。 每个晶体管被配置为将电源电压连接到节点，并且根据存储器操作将节点选择性地耦合到位线。 控制逻辑被配置为使得多个晶体管中的至少一个能够根据来自多个晶体管之一的电源电压的相应阈值电压降向节点提供可编程的预充电电压。

公开(公告)号：US07732922B2

公开(公告)日：2010-06-08

申请号：US11970149

申请日：2008-01-07

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L29/40

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.

摘要翻译： 本发明涉及一种改进的半导体结构，使得在同一绝缘层内嵌入相同绝缘层的Cu互连件具有与嵌入在同一绝缘层中的其它Cu互连不同的Cu晶粒尺寸。

公开(公告)号：US07709365B2

公开(公告)日：2010-05-04

申请号：US11551959

申请日：2006-10-23

申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US20090303812A1

公开(公告)日：2009-12-10

申请号：US12543256

申请日：2009-08-18

申请人： Rajiv V. Joshi ,  Robert Maurice Houle ,  Kevin A. Batson

发明人： Rajiv V. Joshi ,  Robert Maurice Houle ,  Kevin A. Batson

IPC分类号： G11C7/00 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C11/413 ,  G11C11/41 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/1202 ,  G11C2029/1208 ,  H03K5/06 ,  H03K5/13 ,  H03K5/1565

摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

摘要翻译： 本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出​​本地时钟信号的时钟产生电路。 时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。 前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。 后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。