Laser beam induced phenomena detection
    11.
    发明授权
    Laser beam induced phenomena detection 有权
    激光束诱发现象检测

    公开(公告)号:US06897664B1

    公开(公告)日:2005-05-24

    申请号:US10261390

    申请日:2002-09-30

    IPC分类号: G01R31/305 G01R31/311

    CPC分类号: G01R31/311

    摘要: Apparatus for and methods of inspection using laser beam induced alteration are provided. In one aspect, an apparatus is provided that includes a laser scanning microscope for directing a laser beam at a circuit structure and a source for biasing and thereby establishing a power condition in the circuit structure. A detection circuit is provided for detecting a change in the power condition in response to illumination of the circuit structure by the laser beam and generating a first output signal based on the detected change. A signal processor is provided for processing the first output signal and generating a second output signal based thereon. A control system is operable to scan the laser beam according to a pattern that has a plurality of pixel locations, whereby the laser beam may be moved to a given pixel location and allowed to dwell there for a selected time before being moved to another pixel location.

    摘要翻译: 提供了使用激光束诱发改变的装置和检查方法。 在一个方面,提供了一种装置,其包括用于将电路结构的激光束引导的激光扫描显微镜和用于偏置的源,从而在电路结构中建立功率状态。 提供一种检测电路,用于响应于激光束对电路结构的照明而检测功率状态的变化,并且基于检测到的变化产生第一输出信号。 提供信号处理器用于处理第一输出信号并基于此产生第二输出信号。 控制系统可操作以根据具有多个像素位置的图案来扫描激光束,由此激光束可以移动到给定的像素位置,并允许其在移动到另一像素位置之前在选定的时间停留 。

    Electrostatic discharge protection circuitry for any two external pins
of an I.C. package
    12.
    发明授权
    Electrostatic discharge protection circuitry for any two external pins of an I.C. package 失效
    任何两个外部引脚的静电放电保护电路 包

    公开(公告)号:US4870530A

    公开(公告)日:1989-09-26

    申请号:US212282

    申请日:1988-06-27

    IPC分类号: H01L27/06 H01L27/02 H05F3/02

    CPC分类号: H01L27/0248

    摘要: A protective circuit for bipolar integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a plurality of clamping networks (12a-12n). Each of the plurality of clamping networks (12a-12n). is connected between a corresponding one of a number of external input/output pins (P1-Pn) of the integrated circuit and a common bus line (14) which is connected to an external substrate pin (PS). Each of the plurality of clamping networks (12a-12n) includes a silicon-controlled rectifier (T1), a diode (D1), a first resistor (R1) and a second resistor (R2). When any one of the number of external input/output pins (P1-Pn) receives a voltage higher than a predeter-mined value and any remaining one of the external input/output pins (P1-Pn) contacts a ground potential, a discharge path is formed by a single silicon-controlled rectifier and a single diode so as to protect an internal circuit portion.

    Apparatus for metal stack thermal management in semiconductor devices
    14.
    发明授权
    Apparatus for metal stack thermal management in semiconductor devices 有权
    用于半导体器件中金属堆热管理的设备

    公开(公告)号:US06518661B1

    公开(公告)日:2003-02-11

    申请号:US09826576

    申请日:2001-04-05

    IPC分类号: H01L23367

    摘要: A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.

    摘要翻译: 半导体装置包括具有多个有源器件的硅衬底形式的半导体本体。 包括多个金属层的金属堆叠与有源器件可操作地相关联。 多个导电元件以例如印刷电路板的形式连接到金属堆叠和基板。 通孔将导电元件与至少一些金属层的相应部分连接,导电元件连接到衬底内的吸热构件,衬底中的吸热构件又连接到衬底外部的散热器,通孔以规则间隔隔开 从而促进从金属堆叠穿过其到吸热构件和散热器的散热。

    Device analysis for face down chip
    15.
    发明授权
    Device analysis for face down chip 失效
    面向下芯片的器件分析

    公开(公告)号:US5972725A

    公开(公告)日:1999-10-26

    申请号:US988868

    申请日:1997-12-11

    IPC分类号: G01R31/307 H01L29/34

    摘要: A method of precisely measuring electrical parameters in integrated circuits in a face down semiconductor device in which a portion of the semiconductor substrate is removed from the semiconductor device and an SEM microprobe is directed onto selected regions of the surface exposed by the removal of the semiconductor substrate. The microprobe is directed to selected regions of the exposed surface by a computer generated mapping system. One of the selected regions that the microprobe is directed to is a region of the exposed surface overlying a depletion region associated with a drain of a transistor in the semiconductor device. The voltage variation on the exposed surface caused by the expansion and shrinking of the depletion region is measured by the microprobe. Another region that the microprobe is directed to is a region of the exposed surface overlying an insulator and the microprobe detects the voltage of a conducting electrode under the insulator is measured via capacitive coupling. A third region that the microprobe is directed to is a region overlying a reverse-biased junction in the semiconductor device and a change in voltage of the reverse-biased junction is determined by measuring the voltage variation of the depletion region associated with the reverse-biased junction.

    摘要翻译: 一种精确测量半导体器件中的集成电路中的电参数的方法,其中将半导体衬底的一部分从半导体器件移除,并将SEM微探针引导到通过去除半导体衬底而暴露的表面的选定区域上 。 微探针通过计算机生成的测绘系统被引导到暴露表面的选定区域。 微探针被引导到的选定区域中的一个是暴露表面的覆盖与半导体器件中的晶体管的漏极相关联的耗尽区域的区域。 通过微探针测量由耗尽区的膨胀和收缩引起的暴露表面上的电压变化。 微探针引导到的另一个区域是覆盖绝缘体的暴露表面的区域,并且探针通过电容耦合来测量绝缘体下方的导电电极的电压。 微探针被引导到的第三区域是覆盖半导体器件中的反向偏置结的区域和反向偏置结的电压变化,通过测量与反向偏置相关的耗尽区的电压变化来确定 交界处