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公开(公告)号：US09419781B2
公开(公告)日：2016-08-16
申请号：US14563626
申请日：2014-12-08
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US20210152324A1
公开(公告)日：2021-05-20
申请号：US17114348
申请日：2020-12-07
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US10466289B2
公开(公告)日：2019-11-05
申请号：US15699874
申请日：2017-09-08
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC: G01R31/317 , G01R31/3177 , G01R29/26
Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
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公开(公告)号：US20180323951A1
公开(公告)日：2018-11-08
申请号：US15949898
申请日：2018-04-10
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US20170295040A1
公开(公告)日：2017-10-12
申请号：US15499310
申请日：2017-04-27
Applicant: Rambus, Inc.
Inventor： Brian S. Leibowitz , Jaeha Kim
CPC classification number: H04L25/03057 , H03M1/004 , H03M1/123 , H03M1/1245 , H03M1/362 , H04L25/03146 , H04L25/03885 , H04L2025/03363 , H04L2025/03369
Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
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Patent Agency Ranking
公开(公告)号：US20160134442A1
公开(公告)日：2016-05-12
申请号：US14938163
申请日：2015-11-11
Applicant: Rambus Inc.
Inventor： Brian Leibowitz , Jaeha Kim
CPC classification number: H04L25/03057 , H03M1/004 , H03M1/123 , H03M1/1245 , H03M1/362 , H04L25/03146 , H04L25/03885 , H04L2025/03363 , H04L2025/03369
Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
Abstract translation: 在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。 在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。 当前解析的位然后被存储为最近以前解析的位，以准备下一个符号时间。 选择逻辑可以是可编程的，以适应过程，环境和系统变化。
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公开(公告)号：US20150092898A1
公开(公告)日：2015-04-02
申请号：US14563626
申请日：2014-12-08
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC: H04L7/00
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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18.发明授权公开(公告)号：US11022639B2
公开(公告)日：2021-06-01
申请号：US16665179
申请日：2019-10-28
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC: G01R29/26 , G01R31/317
Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
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公开(公告)号：US10432389B2
公开(公告)日：2019-10-01
申请号：US15949898
申请日：2018-04-10
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US09973328B2
公开(公告)日：2018-05-15
申请号：US15209529
申请日：2016-07-13
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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