公开(公告)号：US20240178986A1

公开(公告)日：2024-05-30

申请号：US18516597

申请日：2023-11-21

Applicant: Rambus Inc.

Inventor： Carl W. WERNER ,  Masum HOSSAIN ,  Richelle L. Smith

IPC: H04L7/00

CPC classification number: H04L7/0087 ,  H04L7/0008 ,  H04L7/0091

Abstract: A communication system uses a differential edge modulation scheme having one of four or more values and a clock pulse is also encoded in each unit interval. A four-valued encoding may be as follows: prior to each unit interval, two signals are both at the same value; at the start of the unit interval, a first one of the signals is transitioned to indicate a first bit of the symbol; after a selected one of two delay periods that are less than the unit interval, the other signal to is transitioned indicate a second bit of the symbol; after this transition, both signals are again at the same value. The transitioning, at the start of the unit interval, provides an edge that may be extracted and used a timing reference.

公开(公告)号：US20230253974A1

公开(公告)日：2023-08-10

申请号：US18092564

申请日：2023-01-03

Applicant: Rambus Inc.

Inventor： Masum HOSSAIN ,  Kenneth C. DYER ,  Nhat NGUYEN ,  Shankar TANGIRALA

IPC: H03M1/00 ,  H04L25/03

CPC classification number: H03M1/002 ,  H04L25/03038 ,  H04L25/03 ,  H03M1/007 ,  H03M1/145

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

公开(公告)号：US20190260356A1

公开(公告)日：2019-08-22

申请号：US16276677

申请日：2019-02-15

Applicant: Rambus Inc.

Inventor： Masum HOSSAIN ,  Carl W. WERNER

IPC: H03H11/12 ,  H04B1/04 ,  H04B1/10 ,  H04B1/58

Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

公开(公告)号：US20180054293A1

公开(公告)日：2018-02-22

申请号：US15677467

申请日：2017-08-15

Applicant: Rambus Inc.

Inventor： Masum HOSSAIN ,  Brian Leibowitz ,  Jihong Ren

IPC: H04L7/00 ,  H04L27/32 ,  H04L27/00

CPC classification number: H04L7/0016 ,  H03L7/1974 ,  H03L7/235 ,  H04L7/033 ,  H04L27/0014 ,  H04L27/32 ,  H04L2027/0016 ,  H04L2027/0036 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.