公开(公告)号：US20140149618A1

公开(公告)日：2014-05-29

申请号：US14080724

申请日：2013-11-14

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract translation: 单端接收器耦合到命令和地址（CA）总线的输入 - 输出（I / O）引脚。 接收器可配置双模式I / O支持，以低速摆幅模式和高摆幅模式操作CA总线。 接收器可配置为在高摆幅模式下在I / O引脚上接收第一个命令，响应于第一个命令启动从设备的低速摆动模式的校准，将从设备切换到操作状态 在低速摆动模式下，CA总线保持激活状态，并在低回转模式下在I / O引脚上接收第二个命令。

公开(公告)号：US11803489B2

公开(公告)日：2023-10-31

申请号：US17849450

申请日：2022-06-24

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20230119579A1

公开(公告)日：2023-04-20

申请号：US18082446

申请日：2022-12-15

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US11372784B2

公开(公告)日：2022-06-28

申请号：US16709506

申请日：2019-12-10

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US20200218675A1

公开(公告)日：2020-07-09

申请号：US16709506

申请日：2019-12-10

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US10509741B2

公开(公告)日：2019-12-17

申请号：US16145837

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US09836428B2

公开(公告)日：2017-12-05

申请号：US14411723

申请日：2013-07-17

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Pravin Kumar Venkatesan ,  Yohan Usthavia Frans

IPC: G06F13/42 ,  H03K17/16 ,  G06F13/28 ,  H04L25/02

CPC classification number: G06F13/4221 ,  G06F13/28 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.

公开(公告)号：US20160372210A1

公开(公告)日：2016-12-22

申请号：US15169156

申请日：2016-05-31

Applicant: RAMBUS INC.

Inventor： Pravin Kumar Venkatesan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar ,  Wayne Dettloff

IPC: G11C29/02 ,  G11C11/4099 ,  G11C11/4076 ,  H03M1/66 ,  G11C29/52

CPC classification number: G11C29/023 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4076 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2207/2254 ,  H03M1/66

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract translation: 单端接收器包括用于设定第一内部参考电压（Vref）的内部电压产生电路。 模型电压发生电路可配置为在初始校准期间接收要校准的外部参考电压。 模型电压发生电路可配置为跟踪电压 - 温度（VT）漂移的偏移值，并且在单端接收器的周期性校准期间，将偏移值应用于内部电压产生电路以校准内部Vref。

公开(公告)号：US20230418770A1

公开(公告)日：2023-12-28

申请号：US18216439

申请日：2023-06-29

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  Y02D10/00

Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

公开(公告)号：US20200295974A1

公开(公告)日：2020-09-17

申请号：US16811353

申请日：2020-03-06

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

IPC: H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.