公开(公告)号：US09804931B2

公开(公告)日：2017-10-31

申请号：US14568768

申请日：2014-12-12

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David Secker ,  Ravindranath Kollipara

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/14 ,  G06F1/12 ,  G06F11/20 ,  G06F11/16 ,  G06F13/42

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84

Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US09275733B2

公开(公告)日：2016-03-01

申请号：US14693759

申请日：2015-04-22

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Pradeep Batra ,  Steven Woo ,  Lawrence Lai ,  Chi-Ming Yeung

IPC: G06F5/00 ,  G11C14/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/38 ,  G06F12/06 ,  G11C7/10 ,  G06F12/00 ,  G06F13/42

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

公开(公告)号：US20250061066A1

公开(公告)日：2025-02-20

申请号：US18817173

申请日：2024-08-27

Applicant: Rambus Inc.

Inventor： Vlad Fruchter ,  Keith Lowery ,  George Michael Uhler ,  Steven Woo ,  Chi-Ming (Philip) Yeung ,  Ronald Lee

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

公开(公告)号：US11106542B2

公开(公告)日：2021-08-31

申请号：US16593305

申请日：2019-10-04

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David A. Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F1/12 ,  G06F11/16 ,  G06F11/20 ,  G06F13/42

Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US10437747B2

公开(公告)日：2019-10-08

申请号：US15096111

申请日：2016-04-11

Applicant: Rambus Inc.

Inventor： Vlad Fruchter ,  Keith Lowery ,  George Michael Uhler ,  Steven Woo ,  Chi-Ming (Philip) Yeung ,  Ronald Lee

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

公开(公告)号：US10437685B2

公开(公告)日：2019-10-08

申请号：US15783177

申请日：2017-10-13

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David A. Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F1/12 ,  G06F11/20 ,  G06F11/16 ,  G06F13/42

Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US20180089035A1

公开(公告)日：2018-03-29

申请号：US15783177

申请日：2017-10-13

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David A. Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F11/16

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84 ,  Y02D10/14 ,  Y02D10/151

Abstract: Described is memory system enabling memory minoring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.