公开(公告)号：US06579732B2

公开(公告)日：2003-06-17

申请号：US10027368

申请日：2001-12-20

申请人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

发明人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

IPC分类号： H01L2166

CPC分类号： H01L21/67253 ,  H01L22/12 ,  H01L22/26

摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

公开(公告)号：US06525922B2

公开(公告)日：2003-02-25

申请号：US09751358

申请日：2000-12-29

申请人： Paul Winer ,  Richard H. Livengood ,  Suresh Ramalingam

发明人： Paul Winer ,  Richard H. Livengood ,  Suresh Ramalingam

IPC分类号： H01G4228

CPC分类号： H01L23/49822 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/642 ,  H01L28/90 ,  H01L2224/16 ,  H01L2224/16268 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： A capacitor structure is formed on a substrate member having one or more via holes therein. Metallization portions within the via holes of the substrate member form part of the plates of the capacitor.

公开(公告)号：US6159753A

公开(公告)日：2000-12-12

申请号：US771273

申请日：1996-12-20

申请人： Paul Winer ,  Richard H. Livengood

发明人： Paul Winer ,  Richard H. Livengood

IPC分类号： H01L21/00 ,  H01L21/302 ,  H01L21/44

CPC分类号： H01L21/28562 ,  H01L21/76838 ,  H01L21/76892

摘要： A method and an apparatus for editing an integrated circuit. In one embodiment, an integrated circuit substrate is placed into a laser chemical vapor deposition (LCVD) tool and a conductive metal film is deposited onto the integrated circuit substrate over an area of interest. The integrated circuit substrate is subsequently placed into a focused ion beam (FIB) tool where an optional FIB cleaning step is performed on the conductive element deposited by the LCVD tool to help ensure that a good electrical contact can be made. The FIB tool is also used to introduce any desired cuts into signal lines of the integrated circuit to complete edits. The FIB is also used to remove passivation over integrated circuit nodes of interest to expose buried metal lines for subsequent coupling to the conductive element deposited with the LCVD tool. The FIB tool is then used to deposit a focused ion beam chemical vapor deposition (FIBCVD) conductive element between the exposed integrated circuit nodes of interest and the conductive element deposited with the LCVD tool. As a result, a new conductive element between the nodes of interest is formed through the conductive elements formed by both the LCVD and FIB tools.

摘要翻译： 一种用于编辑集成电路的方法和装置。 在一个实施例中，将集成电路基板放置在激光化学气相沉积（LCVD）工具中，并且在感兴趣的区域上将导电金属膜沉积到集成电路基板上。 集成电路基板随后被放置到聚焦离子束（FIB）工具中，其中在由LCVD工具沉积的导电元件上执行可选的FIB清洁步骤，以帮助确保可以进行良好的电接触。 FIB工具还用于将任何所需的切割引入集成电路的信号线，以完成编辑。 FIB还用于去除感兴趣的集成电路节点上的钝化，以暴露埋入的金属线，以便随后与沉积在LCVD工具上的导电元件耦合。 然后，FIB工具用于在所暴露的感兴趣的集成电路节点和沉积有LCVD工具的导电元件之间沉积聚焦离子束化学气相沉积（FIBCVD）导电元件。 结果，通过由LCVD和FIB工具形成的导电元件形成感兴趣的节点之间的新的导电元件。

公开(公告)号：US6001703A

公开(公告)日：1999-12-14

申请号：US978535

申请日：1997-11-26

申请人： Paul Winer ,  Richard H. Livengood

发明人： Paul Winer ,  Richard H. Livengood

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002 ,  Y10S148/102 ,  Y10S438/975

摘要： A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure. Since the presently described fiducial does not include any contacts in the oxide layer, the additional step of utilizing a focus ion beam mills no longer necessary and the presently described fiducial therefore only needs to be etched with a laser chemical etcher to be exposed.

摘要翻译： 用于对准集成电路管芯的基准。 在一个实施例中，基准被配置为通过激光化学蚀刻通过硅衬底通过C4封装的集成电路管芯的背面暴露。 目前描述的基准包括设置在基板中的浮动扩散区域。 没有金属触点的氧化物层设置在集成电路的基准区域内的扩散区域上。 金属图案层设置在氧化物层下方以提供对准信息。 在从基准区域移除硅衬底之后，金属图案层被配置为通过氧化物层可见。 光块被布置在金属图案层和下面的环氧底层填充层之间以最小化暴露于下面的环氧树脂层的过量光的风险，这使得环氧树脂层不会损害集成电路的风险过大 曝光 由于目前描述的基准点不包括氧化物层中的任何接触，所以利用不再需要的聚焦离子束研磨机的附加步骤因此仅需要用激光化学蚀刻器进行蚀刻来暴露出目前描述的基准。

公开(公告)号：US5948217A

公开(公告)日：1999-09-07

申请号：US771712

申请日：1996-12-20

申请人： Paul Winer ,  Richard H. Livengood

发明人： Paul Winer ,  Richard H. Livengood

IPC分类号： H01J37/305 ,  H01L21/66 ,  C23C14/46 ,  C23C14/34

CPC分类号： B24B37/013 ,  H01J37/3056 ,  H01L22/26 ,  H01J2237/30466 ,  H01L2223/54473

摘要： A method and an apparatus for endpoint determination when milling an integrated circuit disposed in a substrate. In one embodiment, the substrate is charged to a first polarity while the well regions and active diffusion regions of the integrated circuit are charged to another polarity thus resulting in an electrical bias at the P-N junctions in the substrate. By powering up the integrated circuit in this fashion during milling, endpoint detection can be accurately determined by using a voltage contrast mechanism such as the imaging detector of a focused ion beam (FIB) milling tool. A diffusion boundary can also be determined in accordance with the teachings of the invention by the use of the stage current monitor of the FIB milling tool. The diffusion boundary is determined in accordance with the teachings of the present invention by a change in contrast as detected by the imaging detector of the FIB milling tool or by a change in the stage current as measured by the stage current monitor of the FIB milling tool. By accurately determining when a diffusion boundary is reached, the present invention reduces the risk of inadvertently destroying diffusion regions when exposing features in an integrated circuit during debug.

摘要翻译： 一种用于在铣削设置在基板中的集成电路时终端确定的方法和装置。 在一个实施例中，将衬底充电至第一极性，同时将集成电路的阱区和有源扩散区充电至另一极性，从而导致衬底中P-N结的电偏压。 通过在铣削期间以这种方式加电集成电路，可以通过使用诸如聚焦离子束（FIB）铣削工具的成像检测器的电压对比机构来精确地确定端点检测。 扩散边界也可以根据本发明的教导通过使用FIB铣削工具的级电流监视器来确定。 扩散边界根据本发明的教导通过FIB铣刀的成像检测器检测到的对比度变化或通过FIB铣刀的级电流监测器测量的级电流的变化来确定 。 通过精确地确定何时达到扩散边界，本发明降低了在调试期间暴露集成电路中的特征时无意中破坏扩散区的风险。

公开(公告)号：US5942805A

公开(公告)日：1999-08-24

申请号：US771275

申请日：1996-12-20

申请人： Paul Winer ,  Richard H. Livengood

发明人： Paul Winer ,  Richard H. Livengood

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002 ,  Y10S148/102 ,  Y10S438/975

摘要： A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure. Since the presently described fiducial does not include any contacts in the oxide layer, the additional step of utilizing a focus ion beam mill is no longer necessary and the presently described fiducial therefore only needs to be etched with a laser chemical etcher to be exposed.

摘要翻译： 用于对准集成电路管芯的基准。 在一个实施例中，基准被配置为通过激光化学蚀刻通过硅衬底通过C4封装的集成电路管芯的背面暴露。 目前描述的基准包括设置在基板中的浮动扩散区域。 没有金属触点的氧化物层设置在集成电路的基准区域内的扩散区域上。 金属图案层设置在氧化物层下方以提供对准信息。 在从基准区域移除硅衬底之后，金属图案层被配置为通过氧化物层可见。 光块被布置在金属图案层和下面的环氧底层填充层之间以最小化暴露于下面的环氧树脂层的过量光的风险，这使得环氧树脂层不会损害集成电路的风险过大 曝光 由于目前描述的基准不包括氧化物层中的任何接触，所以不再需要利用聚焦离子束研磨机的附加步骤，因此目前描述的基准仅需要用激光化学蚀刻剂进行蚀刻来暴露。

公开(公告)号：US09524681B2

公开(公告)日：2016-12-20

申请号：US13996935

申请日：2011-12-19

申请人： Maximino Vasquez ,  Paul Winer ,  Akihiro Takagi

发明人： Maximino Vasquez ,  Paul Winer ,  Akihiro Takagi

IPC分类号： G09G3/34 ,  G09G3/20

CPC分类号： G09G3/3406 ,  G09G3/2096 ,  G09G2320/064 ,  G09G2320/0646 ,  G09G2330/023 ,  G09G2354/00 ,  G09G2360/16 ,  G09G2370/047 ,  G09G2370/12

摘要： In general, in one aspect, an apparatus receives pixels associated with an image destined for an external display and determines a reduced backlight brightness for the external display and corresponding changes to the pixels to approximate overall quality of the image with current backlight brightness. Backlight commands are generated for the reduced backlight brightness and the pixels are enhanced to correspond to the reduced backlight brightness. The enhanced pixels and the backlight commands are transmitted to the external display via a display interface that supports backlight control. The display interface may be a wireless interface or a wired (cabled) interface (e.g., display port (DP), high definition multimedia interface (HDMI), video graphics array (VGA)). The functionality of the apparatus is included in a computing device so that backlight brightness reductions and corresponding pixel changes can be made taking into account policies of the computing device and user preferences.

摘要翻译： 通常，在一个方面，一种装置接收与去往外部显示器的图像相关联的像素，并且确定用于外部显示器的降低的背光亮度和对像素的对应改变以近似具有当前背光亮度的图像的整体质量。 生成背光灯命令用于降低背光亮度，并增强像素以对应于降低的背光亮度。 增强像素和背光命令通过支持背光控制的显示接口传输到外部显示器。 显示接口可以是无线接口或有线（有线）接口（例如，显示端口（DP），高分辨率多媒体接口（HDMI），视频图形阵列（VGA））。 设备的功能包括在计算设备中，使得可以考虑计算设备的策略和用户偏好来进行背光亮度降低和相应的像素改变。

公开(公告)号：US20060221267A1

公开(公告)日：2006-10-05

申请号：US11092648

申请日：2005-03-29

申请人： Cynthia Bell ,  Thomas Willis ,  Paul Winer ,  Anders Grunnet-Jepsen

发明人： Cynthia Bell ,  Thomas Willis ,  Paul Winer ,  Anders Grunnet-Jepsen

IPC分类号： G02F1/1335

CPC分类号： G02F1/133514 ,  G02F1/136277 ,  H04N9/3108

摘要： A projection display system may use a microdisplay that has pixels that are dedicated to only one narrow wavelength band. A suitable optical filter for each primary display color may be formed from a small number of optical layers, taking advantage of both the rounded profile and narrow range of the emission peaks in a typical projection light source. Thus, groups of pixels may be dedicated to each wavelength band of the display. A planarization layer may be coated on dichroic filter elements that are applied to a cover glass to provide the dedicated wavelengths for each pixel. The planarization layer may smooth out any surface irregularities resulting from the deposition of the dichroic layers on the cover glass.

摘要翻译： 投影显示系统可以使用具有专用于仅一个窄波长带的像素的微显示器。 通过利用典型投影光源中的发光峰值的圆形轮廓和窄范围的优点，可以从少量的光学层形成用于每个主要显示颜色的合适的滤光器。 因此，像素组可以专用于显示器的每个波长带。 平面化层可以涂覆在施加到盖玻璃上以提供每个像素的专用波长的二向色滤光器元件上。 平坦化层可以平滑由于覆盖玻璃上二色性层的沉积而导致的任何表面凹凸。

公开(公告)号：US06878567B2

公开(公告)日：2005-04-12

申请号：US09895127

申请日：2001-06-29

申请人： Paul Winer ,  George P. Vakanas

发明人： Paul Winer ,  George P. Vakanas

IPC分类号： B01L3/00 ,  B81B1/00 ,  B81C1/00 ,  H01L21/00

CPC分类号： H01L21/00 ,  B01L3/5027 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00714 ,  B81C2201/016 ,  Y10S438/94 ,  Y10S438/958

摘要： A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid.

摘要翻译： 公开了一种用于制造钝化微流体结构的方法和装置。 该方法包括提供其中形成有微流体结构的基底。 微流体结构由嵌入层嵌入。 该方法还包括通过在反应性气氛中局部加热微流体结构表面来钝化嵌入的微流体结构，其中钝化的微流体结构适于输送流体。

公开(公告)号：US06617177B1

公开(公告)日：2003-09-09

申请号：US10231392

申请日：2002-08-28

申请人： Paul Winer

发明人： Paul Winer

IPC分类号： H01L2166

CPC分类号： G02F1/1309 ,  G02F1/133351 ,  G02F1/1341 ,  G02F1/136277 ,  G02F2201/42 ,  H01L21/76898

摘要： A method of fabricating LCOS devices and testing them at the wafer-scale to identify known-bad dice, to facilitate completing fabrication of only known-good dice. A wafer-scale transparent electrode glass is temporarily placed over the wafer, and liquid crystal material is injected into the LCOS device cavities through fill holes extending through the wafer. After removing the glass and separating the wafer into dice, only the good dice have their die-scale glass attached, liquid crystal material re-injected, solder bumps affixed, and substrate attached.

摘要翻译： 一种制造LCOS器件的方法，并在晶圆级别进行测试，以识别已知的不良骰子，以便于完成唯一已知的骰子的制造。 将晶片级透明电极玻璃暂时放置在晶片上，并且通过延伸穿过晶片的填充孔将液晶材料注入到LCOS器件腔中。 在去除玻璃并将晶片分离成骰子之后，只有骰子的模具尺寸玻璃被附着，重新注入液晶材料，固定焊料凸块和附着的基板。