Synchronous read channel employing a data randomizer
    12.
    发明授权
    Synchronous read channel employing a data randomizer 失效
    采用数据随机化器的同步读通道

    公开(公告)号:US5844509A

    公开(公告)日:1998-12-01

    申请号:US820926

    申请日:1997-03-19

    摘要: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation. When the Data Randomizer is enabled, the probability of encountering any specific pattern of length n channel bits at a randomly selected location within encoded data is approximately 1/2.sup.n.

    摘要翻译: 公开了一种同步读通道,其从位于磁盘介质上的磁读头读取模拟读信号,根据所需的部分响应对采样值进行滤波,从滤波后的采样值中提取定时信息,并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 读通道采用数据随机化器,其处理未编码的用户数据,以确保具有最坏情况模式灵敏度的信道位模式不会比从随机用户数据预期的更频繁地发生。 数据随机化器采用两个线性反馈移位寄存器:一个产生一个63位的序列,它与每对数据位的MSB相对而言是EXLUSIVE-OR-,另一个产生一个127位的序列,它是独占 每对数据位的LSB。 Data Randomizer不影响错误传播。 当启用数据随机器时,在编码数据内随机选择的位置遇到长度为n个通道位的任何特定模式的概率大约为+ E,fra 1/2 + EE n。

    Gain control circuit for synchronous waveform sampling
    13.
    发明授权
    Gain control circuit for synchronous waveform sampling 失效
    用于同步波形采样的增益控制电路

    公开(公告)号:US5297184A

    公开(公告)日:1994-03-22

    申请号:US12049

    申请日:1993-02-01

    摘要: A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.

    摘要翻译: 一种混合的模拟和数字增益控制电路,用于控制模拟输入信号的幅度。 该电路具有可变增益放大器,其接收来自读/写记录头前置放大器的信号。 可变增益放大器的输出通过多路复用器和均衡器连接到模数转换器,用于在受控采样时将模拟信号转换为数字采样值。 增益控制电路接收指示何时发生脉冲的数字值和脉冲检测器的输出。 增益控制电路内的增益误差检测器确定每个检测脉冲幅度的误差量,并将该误差量滤波并通过数模转换器发送,然后通过取幂电路。 指数电路的输出连接到可变增益放大器的增益控制输入。

    Filtering a read signal to attenuate secondary pulses caused by pole
tips of a thin film magnetic read head
    15.
    发明授权
    Filtering a read signal to attenuate secondary pulses caused by pole tips of a thin film magnetic read head 失效
    滤除读取信号以衰减由薄膜磁头读取头的极尖引起的次脉冲

    公开(公告)号:US5623377A

    公开(公告)日:1997-04-22

    申请号:US222666

    申请日:1994-04-04

    摘要: A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput. Further, the pre-cursor correcting portion of the filter can be disabled in order to avoid delaying the data stream while still canceling the post-cursor secondary pulses. The filter also comprises attenuation and adder means to match the coincident sample values in amplitude and add them to substantially eliminate the effect of the secondary pulses in the discrete data stream.

    摘要翻译: 用于补偿与从磁介质读取的数据产生的离散主脉冲的数据流相关联的离散次级脉冲形成的滤波器。 滤波器的脉冲响应包括具有侧补偿系数的中心系数,用于当输入信号与脉冲响应卷积时衰减次级脉冲。 补偿系数的幅度和延迟可编程,并进行自适应调整,以优化给定环境的脉冲响应。 在传统的FIR实施例中,使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。 在优选实施例中,IIR滤波器仅使用一个延迟线提供两个可编程延迟,从而减小电路的尺寸和成本。 同样在优选实施例中,数据流被交织成偶数和奇数数据流,并且由两个滤波器并行处理,以使吞吐量翻倍。 此外,可以禁用滤波器的前光标校正部分,以避免在仍然取消后光标次级脉冲的同时延迟数据流。 滤波器还包括衰减和加法器装置,以使幅度上重合的采样值相匹配,并将它们相加,以基本上消除离散数据流中次级脉冲的影响。

    Synchronous read channel employing a frequency synthesizer for locking a
timing recovery phase-lock loop to a reference frequency
    17.
    发明授权
    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
    采用频率合成器的同步读通道,用于将定时恢复锁相环锁定到参考频率

    公开(公告)号:US5917668A

    公开(公告)日:1999-06-29

    申请号:US822174

    申请日:1997-03-21

    摘要: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

    摘要翻译: 公开了一种同步读通道,其从位于磁盘介质上的磁读头读取模拟读信号,根据所需的部分响应对采样值进行滤波,从滤波后的采样值中提取定时信息,并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 为了在进入定时恢复采集模式时确保小的频率误差,定时恢复锁相环(PLL)首先被锁定到与写入频率相同的标称读取频率。 这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。 此后,来自读取头的模拟信号被多路复用到定时恢复PLL中,以便获取在用户数据之前记录的获取前导码的实际频率和相位。

    Channel quality circuit employing a test pattern generator in a sampled
amplitude read channel for calibration
    18.
    发明授权
    Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration 失效
    信道质量电路采用采样幅度读取通道中的测试码型发生器进行校准

    公开(公告)号:US6005731A

    公开(公告)日:1999-12-21

    申请号:US844174

    申请日:1997-04-18

    IPC分类号: G11B5/09 G11B20/10 G11B20/18

    摘要: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.

    摘要翻译: 一种信道质量电路,其被并入在磁存储系统中使用的采样幅度读取信道中,用于处理和累积来自各个读取信道分量的性能数据,其中,所述性能数据用于校准所述读取信道以在特定环境中操作, 估计存储系统的误码率,并检测磁介质中的缺陷。 信道质量电路产生写入存储系统的数字数据的测试模式。 然后,当从存储系统读取测试图案时,信道质量电路从读取的信道分量累积性能数据。 测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。 门控逻辑被编程为仅累积感兴趣的特定性能数据。 信道质量电路计算自动和互相关,平方误差和阈值比较。 缺陷检测滤波器检测介质中的特定缺陷。 为了预测存储系统的误码率,信道质量电路将噪声自相关数据,序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。

    Disc storage system with spare sectors dispersed at a regular interval
around a data track to reduced access latency
    19.
    发明授权
    Disc storage system with spare sectors dispersed at a regular interval around a data track to reduced access latency 失效
    具有备用扇区的盘存储系统以规则的间隔围绕数据轨道分散以减少访问延迟

    公开(公告)号:US5844911A

    公开(公告)日:1998-12-01

    申请号:US761993

    申请日:1996-12-12

    摘要: A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment. Then when accessing the track that comprises the defective sector, the data sectors between the defective segment and corresponding spare segment are buffered in a data buffer, and an area in the data buffer is reserved for storing the data associated with the spare segment. In this manner, data can be written to and read from the track in a contiguous sequence without requiring an extra revolution of latency as in the conventional linear replacement defect mapping techniques.

    摘要翻译: 公开了一种用于盘存储系统的缺陷管理系统,其避免了与常规线性替换技术相关联的访问延迟,通过以常规间隔分散每个磁道上的备用段,并在读写操作期间缓冲缺陷扇区与相应备用段之间的扇区。 在一个实施例中,备用段是替换有缺陷的数据扇区的整个扇区; 并且在替代实施例中,备用段仅存储更有效的数据扇区的缺陷部分,而且在实现中更复杂。 在两个实施例中,缺陷管理系统包括用于定位数据扇区内的缺陷段的缺陷定位器。 一旦定位,缺陷管理系统将缺陷扇区(或其缺陷部分)映射到最近的可用备用段。 然后,当访问包括缺陷扇区的轨迹时,将缺陷段与相应的备用段之间的数据扇区缓冲在数据缓冲器中,并且数据缓冲区中的区域被保留用于存储与备用段相关联的数据。 以这种方式,可以以连续的顺序将数据写入轨道并从轨道读取数据,而不需要象传统的线性替换缺陷映射技术那样的等待时间的额外旋转。

    Digital pulse detector
    20.
    发明授权
    Digital pulse detector 失效
    数字脉冲检测器

    公开(公告)号:US5329554A

    公开(公告)日:1994-07-12

    申请号:US879938

    申请日:1992-05-08

    摘要: Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

    摘要翻译: 公开了一种使用四个模拟信号样本的脉冲检测器,一旦超过脉冲信号电平峰值时间的一个采样就检测脉冲。 脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。 脉冲检测器在跟踪数据的同时检测脉冲,并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用用于检测脉冲的替代检测系统。 检测器使用采样信号电平或两个采样的移动平均值进行检测。