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    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency
    12.
    发明授权
    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
    采用频率合成器的同步读通道，用于将定时恢复锁相环锁定到参考频率

    公开(公告)号：US5917668A

    公开(公告)日：1999-06-29

    申请号：US822174

    申请日：1997-03-21

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

    CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

    摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

    摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 为了在进入定时恢复采集模式时确保小的频率误差，定时恢复锁相环（PLL）首先被锁定到与写入频率相同的标称读取频率。 这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。 此后，来自读取头的模拟信号被多路复用到定时恢复PLL中，以便获取在用户数据之前记录的获取前导码的实际频率和相位。

    Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration
    15.
    发明授权
    Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration 失效
    信道质量电路采用采样幅度读取通道中的测试码型发生器进行校准

    公开(公告)号：US6005731A

    公开(公告)日：1999-12-21

    申请号：US844174

    申请日：1997-04-18

    申请人： William R. Foland, Jr. ,  Richard T. Behrens ,  Alan J. Armstrong ,  Neal Glover

    发明人： William R. Foland, Jr. ,  Richard T. Behrens ,  Alan J. Armstrong ,  Neal Glover

    IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/18

    CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/18 ,  G11B20/1816 ,  G11B20/182 ,  G11B5/09

    摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.

    摘要翻译： 一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作， 估计存储系统的误码率，并检测磁介质中的缺陷。 信道质量电路产生写入存储系统的数字数据的测试模式。 然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。 测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。 门控逻辑被编程为仅累积感兴趣的特定性能数据。 信道质量电路计算自动和互相关，平方误差和阈值比较。 缺陷检测滤波器检测介质中的特定缺陷。 为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。

    Disc storage system with spare sectors dispersed at a regular interval around a data track to reduced access latency
    16.
    发明授权
    Disc storage system with spare sectors dispersed at a regular interval around a data track to reduced access latency 失效
    具有备用扇区的盘存储系统以规则的间隔围绕数据轨道分散以减少访问延迟

    公开(公告)号：US5844911A

    公开(公告)日：1998-12-01

    申请号：US761993

    申请日：1996-12-12

    申请人： John Schadegg ,  Neal Glover ,  Laura Droege Shellhamer ,  William L. Witt ,  Richard T. Behrens

    发明人： John Schadegg ,  Neal Glover ,  Laura Droege Shellhamer ,  William L. Witt ,  Richard T. Behrens

    IPC分类号： G11B7/007 ,  G11B20/18 ,  G01R31/28 ,  G11B7/00

    CPC分类号： G11B20/1883 ,  G11B2220/20 ,  G11B7/007

    摘要： A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment. Then when accessing the track that comprises the defective sector, the data sectors between the defective segment and corresponding spare segment are buffered in a data buffer, and an area in the data buffer is reserved for storing the data associated with the spare segment. In this manner, data can be written to and read from the track in a contiguous sequence without requiring an extra revolution of latency as in the conventional linear replacement defect mapping techniques.

    摘要翻译： 公开了一种用于盘存储系统的缺陷管理系统，其避免了与常规线性替换技术相关联的访问延迟，通过以常规间隔分散每个磁道上的备用段，并在读写操作期间缓冲缺陷扇区与相应备用段之间的扇区。 在一个实施例中，备用段是替换有缺陷的数据扇区的整个扇区; 并且在替代实施例中，备用段仅存储更有效的数据扇区的缺陷部分，而且在实现中更复杂。 在两个实施例中，缺陷管理系统包括用于定位数据扇区内的缺陷段的缺陷定位器。 一旦定位，缺陷管理系统将缺陷扇区（或其缺陷部分）映射到最近的可用备用段。 然后，当访问包括缺陷扇区的轨迹时，将缺陷段与相应的备用段之间的数据扇区缓冲在数据缓冲器中，并且数据缓冲区中的区域被保留用于存储与备用段相关联的数据。 以这种方式，可以以连续的顺序将数据写入轨道并从轨道读取数据，而不需要象传统的线性替换缺陷映射技术那样的等待时间的额外旋转。

    Digital pulse detector
    17.
    发明授权
    Digital pulse detector 失效
    数字脉冲检测器

    公开(公告)号：US5329554A

    公开(公告)日：1994-07-12

    申请号：US879938

    申请日：1992-05-08

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    IPC分类号： G11B20/10 ,  G11B20/14 ,  H03K5/1532 ,  H03K5/19 ,  H04L25/08 ,  H04L27/00 ,  H04L27/06

    CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/1403 ,  H03K5/19

    摘要： Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

    摘要翻译： 公开了一种使用四个模拟信号样本的脉冲检测器，一旦超过脉冲信号电平峰值时间的一个采样就检测脉冲。 脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。 脉冲检测器在跟踪数据的同时检测脉冲，并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用用于检测脉冲的替代检测系统。 检测器使用采样信号电平或两个采样的移动平均值进行检测。

    Method and apparatus for reduced-complexity viterbi-type sequence detectors
    18.
    发明授权
    Method and apparatus for reduced-complexity viterbi-type sequence detectors 失效
    复杂度维特比型序列检测器的方法和装置

    公开(公告)号：US5291499A

    公开(公告)日：1994-03-01

    申请号：US852015

    申请日：1992-03-16

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Neal Glover

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Neal Glover

    IPC分类号： G06F11/30 ,  G06F11/10 ,  G11B20/14 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M7/14 ,  H03M13/23 ,  H03M13/41 ,  H04B3/04 ,  H04L25/08 ,  H04L25/49 ,  H04L25/497 ,  H04L27/00 ,  G06F11/00

    CPC分类号： G11B20/1426 ,  G11B20/1833 ,  H03M13/41 ,  H03M13/4107 ,  H04L25/4906 ,  H04L25/497

    摘要： A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator. The invention supports a wide range of sample models by making the expected sample sequence of an isolated medium transition programmable. The invention reduces the speed at which the detector circuitry must operate relative to the sample rate by allowing multiple samples to be processed simultaneously. Several reduced detectors for specific sample sequence models are presented for particular applications. The invention is applicable to other types of Viterbi detectors, such as decoders for convolutional codes.

    摘要翻译： 修改维特比检测器以减少其实现复杂度。 部分响应信号可以被视为从有限状态机模型生成的预期样本的序列。 在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差 度量，并选择具有最低路径错误度量的路径。 在本发明中，ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。 这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。 与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块而没有显着的性能损失。 本发明通过使分离的介质跃迁的预期采样序列可编程化来支持范围广泛的样本模型。 本发明通过允许同时处理多个采样来降低检测器电路相对于采样率运行的速度。 针对特定应用提出了特定样品序列模型的几种降低检测器。 本发明可应用于其它类型的维特比检测器，例如用于卷积码的解码器。

    Synchronous read channel
    19.
    发明授权
    Synchronous read channel 有权

    公开(公告)号：US07885255B2

    公开(公告)日：2011-02-08

    申请号：US12126188

    申请日：2008-05-23

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    IPC分类号： H04L12/50

    摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

    Synchronous read channel
    20.
    发明授权
    Synchronous read channel 失效
    同步读通道

    公开(公告)号：US07379452B2

    公开(公告)日：2008-05-27

    申请号：US10028871

    申请日：2001-12-21

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    IPC分类号： H04L12/50

    CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

    摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

    摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特性，容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。 公开了包括在单个集成电路中并入模拟量以及读取通道的数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂性的可编程修改维特比检测器的实施例。