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公开(公告)号：US08716776B2
公开(公告)日：2014-05-06
申请号：US13533099
申请日：2012-06-26
IPC分类号： H01L29/12
CPC分类号： H01L21/2007 , G06F17/5068 , H01L21/76224 , H01L21/7624 , H01L21/76251 , H01L21/76283 , H01L21/84 , H01L27/0207 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L27/1203 , H01L28/40 , H01L28/90 , H01L29/66181
摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
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公开(公告)号：US07927968B2
公开(公告)日：2011-04-19
申请号：US12125106
申请日：2008-05-22
申请人： Deok-Kee Kim , Seong-Dong Kim , Oh-Jung Kwon
发明人： Deok-Kee Kim , Seong-Dong Kim , Oh-Jung Kwon
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846 , Y10S257/908
摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.
摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。
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13.发明申请METHOD OF SILICIDE FORMATION BY ADDING GRADED AMOUNT OF IMPURITY DURING METAL DEPOSITION 失效通过在金属沉积期间增加放射量的量来制备硅化物的方法公开(公告)号：US20110070732A1
公开(公告)日：2011-03-24
申请号：US12563459
申请日：2009-09-21
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , C23C14/18 , C23C14/5806 , H01L21/2855
摘要： A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.
摘要翻译： 提供一种用于形成金属半导体合金的方法，其包括提供包括铂源和镍源的沉积设备，其中所述铂源与所述镍源分离; 将具有半导体表面的基板定位在沉积设备中; 在半导体表面上形成金属合金，其中形成金属合金包括沉积阶段，其中铂源以最初的速率以最初的速率将铂沉积到半导体表面上，该初始时间段大于最终时间段的最终时间 沉积阶段，镍源将镍沉积到半导体表面; 并退火金属合金以使镍和铂与半导体衬底反应以提供镍铂半导体合金。
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公开(公告)号：US07670901B2
公开(公告)日：2010-03-02
申请号：US12033984
申请日：2008-02-20
IPC分类号： H01L21/762
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.
摘要翻译： 制造瓶沟槽和瓶沟电容器的方法。 该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。
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15.发明申请Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance 有权形成具有低接触电阻的硅化源/漏极触点的场效应晶体管的方法公开(公告)号：US20090239344A1
公开(公告)日：2009-09-24
申请号：US12402816
申请日：2009-03-12
申请人： Yong Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
发明人： Yong Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
IPC分类号： H01L21/335 , H01L21/28
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833
摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。
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公开(公告)号：US20080220587A1
公开(公告)日：2008-09-11
申请号：US12125106
申请日：2008-05-22
申请人： Deok-kee Kim , Seong-Dong Kim , Oh-Jung Kwon
发明人： Deok-kee Kim , Seong-Dong Kim , Oh-Jung Kwon
IPC分类号： H01L21/762
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846 , Y10S257/908
摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.
摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。
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公开(公告)号：US07387930B2
公开(公告)日：2008-06-17
申请号：US11458120
申请日：2006-07-18
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.
摘要翻译： 制造瓶沟槽和瓶沟电容器的方法。 该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。
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18.发明申请Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method 审中-公开具有包含氘底物的隔离结构的结构及相关方法公开(公告)号：US20070259500A1
公开(公告)日：2007-11-08
申请号：US11381861
申请日：2006-05-05
申请人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
发明人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
IPC分类号： H01L21/336 , H01L21/76 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/3003 , H01L21/76283 , H01L21/823481 , H01L29/66772 , H01L29/78 , H01L29/78654
摘要： Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation structure within the substrate, the isolation structure including substantially uniformly distributed deuterium in a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. The substrate may include a semiconductor-on-insulator substrate. A method may include the steps of: providing an isolation structure in a substrate, the isolation structure including deuterium; and annealing to diffuse the deuterium into the substrate (prior to and/or after forming a gate dielectric). The structures and method provide a more efficient means for incorporating deuterium and reducing defects. In addition, the deuterium anneal can occur prior to gate dielectric formation during front-end-of-line processes, such that the anneal temperature can be high to improve deuterium incorporation with reduced anneal time.
摘要翻译： 公开了具有包括氘的隔离结构的结构和相关方法。 氘优选基本上均匀分布，并且具有大于在天然存在的氢气中发现的浓度（基于总氢原子含量）。 一种结构包括用于半导体器件的衬底，该衬底包括衬底内的隔离结构，该隔离结构包括基本上均匀分布的氘，其浓度（基于总氢原子含量）大于在天然存在的氢中发现的浓度。 衬底可以包括绝缘体上半导体衬底。 一种方法可以包括以下步骤：在衬底中提供隔离结构，所述隔离结构包括氘; 和退火以将氘扩散到衬底中（在形成栅极电介质之前和/或之后）。 结构和方法提供了一种更有效的方法来引入氘和减少缺陷。 此外，氘退火可以在前端工艺过程中的栅极电介质形成之前发生，使得退火温度可以高以改善氘掺杂并减少退火时间。
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公开(公告)号：US08652925B2
公开(公告)日：2014-02-18
申请号：US12838515
申请日：2010-07-19
IPC分类号： H01L21/20
CPC分类号： H01L21/2007 , G06F17/5068 , H01L21/76224 , H01L21/7624 , H01L21/76251 , H01L21/76283 , H01L21/84 , H01L27/0207 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L27/1203 , H01L28/40 , H01L28/90 , H01L29/66181
摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。
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公开(公告)号：US08633520B2
公开(公告)日：2014-01-21
申请号：US12909002
申请日：2010-10-21
申请人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
发明人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L23/52
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76813 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.
摘要翻译： 提供半导体器件。 半导体器件包括：衬底; 在衬底中形成的器件隔离区; 在每隔两个相邻的器件隔离区域之间形成在衬底的区域中的杂质区; 形成在所述基板上的栅电极; 顺序形成在基板上的第一和第二层间绝缘膜; 形成在所述第二层间绝缘膜上并且包括金属布线层的金属层间绝缘膜; 电连接每个金属布线层和杂质区的第一接触插塞; 以及第二接触插塞，其电连接每个所述金属布线层和所述栅电极，其中所述第一接触插塞形成在所述第一和第二层间绝缘膜中，并且所述第二接触插塞形成在所述第二层间绝缘膜中。
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