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公开(公告)号：US20090094496A1
公开(公告)日：2009-04-09
申请号：US11866787
申请日：2007-10-03
IPC分类号： G06F11/25
CPC分类号： G06F11/27
摘要： A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets.A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
摘要翻译： 一种用于改进逻辑内置自检（LBIST）的方法包括：由LBIST控制器将多个控制信号组提供给包括多个LBIST卫星模块的LBIST域。 多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描和LBIST序列操作。 测试系统包括包括多个LBIST卫星模块的逻辑内置自测（LBIST）域。 LBIST控制器耦合到LBIST域并向LBIST域提供多个控制信号组，其中多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描操作。
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12.发明授权公开(公告)号：US07266463B2
公开(公告)日：2007-09-04
申请号：US11126120
申请日：2005-05-10
IPC分类号： G01R19/00
CPC分类号： G01R31/3167 , G01R31/31924
摘要： An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.
摘要翻译： 提供了用于识别模拟电气系统中的信号的装置，方法和计算机程序产品。 控制该信号识别电路的定时的ID选择信号包括向上计数并识别相应信号的顺序号码。 要识别的信号位于一组输入/输出（I / O）引脚上。 一个多路复用器（第一）响应于ID选择信号选择一个特定的I / O引脚。 隔离电压源连接到该多路复用器，并将所选择的信号提供给另一个多路复用器（第二）。 响应于ID选择信号，第二多路复用器从该隔离电压源切换到接地电位。 隔离电压源浮动在所选I / O驱动器引脚的直流电平上。 因此，通过连接到所选信号的I / O引脚和第二多路复用器的输出，可以识别所选择的信号，然后探测。
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13.发明授权公开(公告)号：US06820226B2
公开(公告)日：2004-11-16
申请号：US10042097
申请日：2002-01-07
IPC分类号： G01R3128
CPC分类号： G06F11/26 , G01R31/31924
摘要： In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.
摘要翻译： 在本发明的一个方面，一种用于测试的方法包括在第一和第二逻辑之间插入测试器。 第一逻辑和第二逻辑具有相应的第一和第二输出驱动器。 测试仪在测试周期中操作以响应于在一个测试周期期间由第一驱动器所确定的信号和在紧随其后的一个测试周期期间由第二驱动器断言的信号来检测动态争用。 在一个测试周期期间响应于由第一驱动器确定的信号来检测静态争用，以及在同一个测试周期期间由第二驱动器断言的信号。
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公开(公告)号：US6125467A
公开(公告)日：2000-09-26
申请号：US63962
申请日：1998-04-21
IPC分类号： G06F11/10
CPC分类号： G06F11/1012 , G06F11/1052
摘要： A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits. The undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.
摘要翻译： 一种在计算机系统的通信路径中传送通过纠错码（ECC）块的方法。 通信路径使用第一粒度将计算机系统的第一组件（诸如随机存取存储器（RAM）设备）和计算机系统的第二组件（诸如中央处理单元（CPU））互连，并且 第三组件（例如只读存储器（ROM）设备）进一步连接到通信路径，使得第三组件可以使用小于第一粒度的第二粒度将数据发送到第二组件。 来自第三组件的数据通过将来自第三组件的数据与预定义数据合并，将合并的数据字呈现给ECC电路，其中合并的数据字具有第一粒度。 第一粒度可以是例如72位，而第二粒度可以是8位。 优先使用多个相应的上拉电阻将未驱动的校验位和未驱动的数据位强制为预定状态。
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公开(公告)号：US20090210566A1
公开(公告)日：2009-08-20
申请号：US12032990
申请日：2008-02-18
IPC分类号： G06F3/00
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译： 本发明提供一种系统。 该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号 通过输出引脚基于自识别控制信号。 每个输出引脚耦合到外部系统。 处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。
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公开(公告)号：US07275199B2
公开(公告)日：2007-09-25
申请号：US10912483
申请日：2004-08-05
IPC分类号： G11C29/52
CPC分类号： G06F11/1032
摘要： A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.
摘要翻译： 提供了一种方法，装置和计算机程序，用于顺序地确定存储的数据的奇偶性。 由于大多数内存阵列中存在固有的不稳定性，数据损坏可能是一个重大问题。 通常采用奇偶校验和其他技术来解决问题。 然而，通过奇偶校验和其他技术，有权衡。 例如，执行奇偶校验所需的时间可能会导致系统延迟。 因此，为了减少延迟，信任寄存器可以被包括在存储器系统中以允许立即访问一条可信数据。 通过能够读取一条可信赖的数据，系统可以通过从存储器阵列读取数据的下一个位置来重叠数据位置的奇偶校验和传送。 因此，可以消除整个周期的延迟，而不降低时钟频率。
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公开(公告)号：US5768573A
公开(公告)日：1998-06-16
申请号：US753119
申请日：1996-11-20
CPC分类号： G06F1/14
摘要： A method and apparatus for generating a divisor having a variable value for real time calculations. A microprocessor's time base register is used to generate the divisor. All interrupts and refreshes are disabled on the microprocessor before calculating the divisor. The microprocessor's time base register is cleared and allowed to count the number of clock ticks in a one second interval. The time base register is read and the value used as a divisor for real time calculations.
摘要翻译： 一种用于生成具有用于实时计算的可变值的除数的方法和装置。 微处理器的时基寄存器用于产生除数。 在计算除数之前，微处理器上的所有中断和刷新都被禁止。 微处理器的时基寄存器被清除，并允许在一秒钟的时间间隔内对时钟脉冲数进行计数。 读取时基寄存器，将该值用作实时计算的除数。
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18.发明授权Multi-chip digital system having a plurality of controllers with self-identifying signal 失效具有多个具有自识别信号的控制器的多芯片数字系统公开(公告)号：US08020058B2
公开(公告)日：2011-09-13
申请号：US12032990
申请日：2008-02-18
IPC分类号： G01R31/28
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译： 本发明提供一种系统。 该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号 通过输出引脚基于自识别控制信号。 每个输出引脚耦合到外部系统。 处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。
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公开(公告)号：US07737763B2
公开(公告)日：2010-06-15
申请号：US11674238
申请日：2007-02-13
IPC分类号： H01H37/76
摘要： A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to a virtual blown state.
摘要翻译： 公开了允许电子熔断器的状态从未吹制状态改变到吹制状态然后回到虚拟未吹塑状态的虚拟电子熔断器装置和方法。 在一个实施例中，电子熔断器可以从虚拟未吹制状态改变到虚拟吹制状态。
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20.发明授权Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted 失效具有多个具有输入和输出引脚的控制器的多芯片数字系统，其中接收和发送自识别信号公开(公告)号：US07409469B2
公开(公告)日：2008-08-05
申请号：US10870459
申请日：2004-06-17
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.
摘要翻译： 本发明提供一种包括控制器和处理器的系统。 所述控制器至少包括输出引脚和多个输入引脚，并且被配置为通过所述多个输入引脚中的一个或多个接收自识别控制信号，并且基于所述输出引脚基于所述输出引脚传输控制器自识别信号 自我识别控制信号。 处理器耦合到控制器并被配置为产生自识别控制信号并将自识别控制信号发送到控制器。
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