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公开(公告)号：US5343096A
公开(公告)日：1994-08-30
申请号：US885584
申请日：1992-05-19
IPC分类号： G11C11/409 , G01R31/30 , H03K19/003 , H03K19/096
CPC分类号： H03K19/00384 , G01R31/30 , H03K19/096
摘要： The present invention tolerates the decay of a dynamic logic circuit by preserving the logic state of the output before the decay. A slow clock detector is configured to detect a slow clock condition of the clock pertaining to the dynamic logic circuit. A tolerant storage device is configured to preserve the data output by command of the slow clock detector upon a detection of the slow clock condition.
摘要翻译： 本发明通过在衰减之前保持输出的逻辑状态来容忍动态逻辑电路的衰减。 慢时钟检测器被配置为检测与动态逻辑电路相关的时钟的慢时钟条件。 容忍存储装置被配置为在检测到慢时钟条件时保留由慢时钟检测器的命令输出的数据。
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12.发明授权
公开(公告)号：US5329176A
公开(公告)日：1994-07-12
申请号：US137902
申请日：1993-09-29
IPC分类号： G06F7/50 , G06F7/501 , H03K19/094 , H03K19/096 , H03K19/21 , H03K19/017
CPC分类号： G06F7/5016 , H03K19/094 , H03K19/0966 , H03K19/215
摘要： A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.
摘要翻译： 为具有级联自定时动态逻辑门的逻辑块提供时钟系统和方法。 动态逻辑门并行预充电，并对矢量输入进行自定时逻辑评估，以得出矢量输出。 评估完成检测器监视逻辑块的输出，并确定矢量输出何时有效。 边缘检测器检测任意周期性定时信号的上升沿和下降沿。 最后，由边缘检测器设置逻辑块时钟发生器并由评估完成检测器复位，以便向逻辑块提供预充电信号，从而定义相应的预充电周期，并且提供用于自适应逻辑评估的评估周期 逻辑块。 在具体实现中，逻辑评估的速度是系统时钟速度的两倍。
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公开(公告)号：US5740181A
公开(公告)日：1998-04-14
申请号：US662403
申请日：1996-06-12
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318522
摘要： The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.
摘要翻译： 通过在连续的时钟周期内将两组或更多组数据发送到流水线来观察流水线的操作。 时钟自由运行，因为它需要数据传播通过管道的阶段。 只有当感兴趣的数据分别保存在每个输出锁存器中时，才会对流水线的每一级的输出锁存器进行采样。 观察可以通过标准测试访问端口（TAP）完全控制。 观察可以通过暂停时钟来扫描新数据并导出，或者与时钟自由运行来实现。 管道的输入可能来自测试寄存器或来自在正常操作期间馈送流水线的电路。
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14.发明授权
公开(公告)号：US5691652A
公开(公告)日：1997-11-25
申请号：US603977
申请日：1996-02-20
IPC分类号： H01L27/04 , H01L21/822 , H03K3/356 , H03K19/00 , H03K19/003 , H03K19/096 , H03K17/16
CPC分类号： H03K19/00338 , H03K3/35606
摘要： A system and method for improving alpha-particle induced soft error rates in integrated circuits is provided. Logic isolation circuits implemented using a substantially fewer number of pn-junctions are situated at the outputs of fast logic portions containing a substantially greater number of pn-junctions. The present invention reduces the vulnerability of a dynamic logic circuit of incurring alpha soft errors by effectively trading the probability of an isolation circuit composed of only a few pn-junctions incurring alpha-particle strikes with the probability of a fast logic circuit having substantially more pn-junctions incurring alpha-particle strikes. By reducing the number of pn-junctions susceptible to alpha-particle strikes, the present invention significantly lowers the potential alpha-particle induced soft error rate. In one embodiment, isolation circuits used in the present invention are implemented using self-timed logic, to reduce the window in which a circuit is logically vulnerable to alpha strikes, in which a loss of state can occur.
摘要翻译： 提供了一种用于提高集成电路中α粒子诱导的软错误率的系统和方法。 使用基本上较少数量的pn结实现的逻辑隔离电路位于包含基本上更多数量的pn结的快速逻辑部分的输出处。 本发明通过有效地交换由仅具有几个pn结组成的隔离电路的概率来降低产生阿尔法软错误的动态逻辑电路的脆弱性，其中快速逻辑电路具有基本上更多的pn的概率 - 引起α粒子撞击的结点。 通过减少易受α-粒子撞击的pn结的数量，本发明显着降低了潜在的α粒子诱导的软错误率。 在一个实施例中，本发明中使用的隔离电路使用自定时逻辑来实现，以减少电路逻辑上容易受到可能发生状态损失的α打击的窗口。
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公开(公告)号：US5557620A
公开(公告)日：1996-09-17
申请号：US533415
申请日：1995-09-25
IPC分类号： G01R31/26 , G01R31/30 , G01R31/317 , H01L21/66 , G06F11/00
CPC分类号： G01R31/3004
摘要： A system and method for quiescent current testing of dynamic logic circuitry. Nodes shorted to ground are detected during a dynamic pre-charge state. Nodes shorted to a power supply potential are detected by driving all nodes of interest to ground during a dynamic evaluation phase. Nodes of interest are driven to ground directly by one additional transistor per node or indirectly by logical propagation from upstream nodes. As a result, only two current measurements are needed for all shorted node faults, even for pipelined systems with multiple clocks. There is no need for input test signal sequences and no need for signal propagation to outputs for detection. Specific embodiments are provided for single-rail logic, single-rail pipelined systems, dual-rail logic and dual-rail pipelined systems. For single-rail pipelined systems, optional transistors between stages enable preservation of logical states during testing. For dual-rail logic, storage nodes and static nodes are forced to a logical state that is not possible during normal operation. For pipelined dual-rail logic, testing of alternate stages inherently preserves the logical state of the system during testing.
摘要翻译： 一种静态电流测试动态逻辑电路的系统和方法。 在动态预充电状态期间检测到接地短路的节点。 通过在动态评估阶段将感兴趣的所有节点驱动到地面来检测短路到电源电位的节点。 感兴趣的节点通过每个节点的一个附加晶体管直接驱动到地，或间接通过来自上游节点的逻辑传播。 因此，即使对于具有多个时钟的流水线系统，所有短路节点故障都只需要两个电流测量。 不需要输入测试信号序列，不需要信号传播到输出进行检测。 为单轨逻辑，单轨流水线系统，双轨逻辑和双轨流水线系统提供具体实施例。 对于单轨流水线系统，阶段之间的可选晶体管能够在测试期间保持逻辑状态。 对于双轨逻辑，存储节点和静态节点被强制为在正常操作期间不可能的逻辑状态。 对于流水线双轨逻辑，替代阶段的测试固有地保留系统在测试期间的逻辑状态。
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公开(公告)号：US5057701A
公开(公告)日：1991-10-15
申请号：US479562
申请日：1990-02-13
IPC分类号： H03K3/353 , H03K3/356 , H03K3/3565 , H03K5/151
CPC分类号： H03K3/356113 , H03K3/3565 , H03K5/151
摘要： A clock buffer circuit achieves insensitivity to the particular voltage levels and drift therein of input signals used to generate the clock, by use of a differential common gate amplifier incorporating an internally generated threshold voltage. Four separate gain paths couple the differential common gate amplifier to an output stage. Two of the gain paths are used to propagate edges that cause respective abrupt transitions in each direction for a first of two complementary clock signals. The other two accomplish the same for the other complementary clock signal. Each gain path is optimized to propagate a leading edge of a particular direction (relative to its point of origin, the direction of the edge inverts as it goes from stage to stage). Of these four gain paths, a first pair are used to create a high level of drive for the low to high transitions in the clock signal and its complement. Because of the optimization, this drive cannot be removed as abruptly as it can be applied. A latch-like circuit in the gain paths cause early removal of the high level, or hard, drive, leaving in place a maintenance, or holding, level of drive. Each holding drive is abruptly removed by an associated gain path in the remaining pair of gain paths. The hard drive is left in place only long enough to ensure that the capacitance of the clock line is adequately charged. An anti-glitch mechanism bullet proofs the entire circuit against drive fights caused by ambiguities arising from slow transitions that might arise from the differential common gate amplifier.
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