公开(公告)号：US5485106A

公开(公告)日：1996-01-16

申请号：US222988

申请日：1994-04-05

申请人： Robert J. Drost ,  David M. Murata ,  Robert J. Bosnyak ,  Mark R. Santoro ,  Lee S. Tavrow

发明人： Robert J. Drost ,  David M. Murata ,  Robert J. Bosnyak ,  Mark R. Santoro ,  Lee S. Tavrow

IPC分类号： H03K3/021 ,  H03K17/567 ,  H03K19/0175 ,  H03K19/082 ,  H03K19/0948

CPC分类号： H03K17/567 ,  H03K19/017563 ,  H03K3/021

摘要： An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability. In this embodiment, each output driver includes a CMOS inverter pair and a bipolar transistor coupled between the respective output node of the driver and V.sub.DD.

摘要翻译： 用于BiCMOS集成电路的高效ECL至CMOS逻辑转换器。 在一个实施例中，差分放大器将ECL输入信号与ECL参考电压进行比较，并在对应的差分输出节点对上生成一对互补中间信号。 差分放大器具有与公共负载电阻串联耦合的两个负载电阻，其限制差分输出节点处的高电压摆幅。 耦合到差分输出节点的再生级响应于互补的中间信号在部分导通状态和完全导通状态之间切换。 一对反相器级将互补的中间信号转换为一对CMOS电平信号。 耦合到相应的互补反相器级的一对互补输出驱动器提供电流驱动能力。 在本实施例中，每个输出驱动器包括耦合在驱动器的相应输出节点与VDD之间的CMOS反相器对和双极晶体管。

公开(公告)号：US06396308B1

公开(公告)日：2002-05-28

申请号：US09795281

申请日：2001-02-27

申请人： Robert J. Bosnyak ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03F345

CPC分类号： G11C7/065 ,  G11C2207/005

摘要： A sense amplifier having dual differential inputs configured to accept differential analog input voltages. The differential analog input voltages are fused to determine a weighted signal digitally representative of the differential analog input voltages. An input offset voltage cancellation circuit may be coupled to the sense amplifier to reduce an input offset voltage of the sense amplifier.

摘要翻译： 具有双差分输入的读出放大器被配置为接受差分模拟输入电压。 差分模拟输入电压被融合以确定数字代表差分模拟输入电压的加权信号。 输入偏移电压消除电路可以耦合到读出放大器以减小读出放大器的输入偏移电压。

公开(公告)号：US6084452A

公开(公告)日：2000-07-04

申请号：US107898

申请日：1998-06-30

申请人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

IPC分类号： H03K5/156 ,  H03K3/017

CPC分类号： H03K5/1565

摘要： An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal. The duty cycle error measurement circuit rejects the common mode of the reference and comparison signals and passes the differential mode of the reference and comparison signals to generate a duty cycle adjust signal responsive to receiving the reference and comparison signals. The duty cycle adjuster is coupled to receive an input clock signal and the duty cycle adjust signal and to provide the single-ended clock signal. The single-ended clock signal has a duty cycle determined at least in part by the duty cycle adjust signal.

摘要翻译： 一个装置调整单端时钟信号的占空比。 单端时钟信号在第一和第二电压之间振荡。 该装置包括误差指示电路，占空比误差测量电路和占空比调节器。 误差指示电路包括参考电路和比较电路。 参考电路耦合到具有第一电压的第一节点和具有第二电压的第二节点以从第一和第二电压产生参考信号。 参考电路包括第一电特征单元的至少一个实例。 比较电路被耦合以接收反馈时钟信号并从其产生比较信号。 比较电路包括第一电特征单元的至少一个实例。 负载周期误差测量电路被耦合以接收参考信号和比较信号。 占空比误差测量电路拒绝参考和比较信号的共模，并通过参考和比较信号的差分模式，以响应于接收参考和比较信号产生占空比调整信号。 负载周期调节器被耦合以接收输入时钟信号和占空比调整信号并提供单端时钟信号。 单端时钟信号具有至少部分由占空比调整信号确定的占空比。

公开(公告)号：US6020765A

公开(公告)日：2000-02-01

申请号：US866653

申请日：1997-05-30

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03K5/26 ,  H03L7/085 ,  H03L7/087 ,  H04L7/033 ,  H04L25/40 ,  H03D13/00

CPC分类号： H03L7/085 ,  H04L7/033

摘要： A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal. It is also preferred that the error pulses have a repetition rate that corresponds to the edges of the NRZ signal, a current amplitude that is proportional to the frequency difference between the NRZ signal and the reference signal, and a polarity that represents a sign of the frequency difference between the NRZ signal and the reference signal. The frequency difference detector is well-suited for use in a frequency/phase-locked loop that provides a clock recovery circuit.

摘要翻译： 频率差检测器包括脉冲发生器，其接收NRZ信号和参考信号，并且基于参考信号的边缘提供基于NRZ信号和第二边缘的第一边缘的数据脉冲，脉冲路由器将连续的 数据脉冲到不同的信号路径，电压发生器，其从信号路径接收数据脉冲，并提供基于数据脉冲的脉冲宽度的幅度的电压信号;以及比较电路，其接收电压信号并提供具有幅度的误差脉冲 基于电压信号之间的电压差。 误差脉冲的振幅表示NRZ信号和参考信号之间的频率差。 优选地，数据脉冲具有基于NRZ信号的边缘的前沿，并且基于紧跟NRZ信号的边缘的参考信号的前沿之后的滞后边缘。 还优选地，误差脉冲具有对应于NRZ信号的边缘的重复率，与NRZ信号和参考信号之间的频率差成比例的电流幅度，以及表示该NRZ信号的符号的极性 NRZ信号与参考信号之间的频率差。 频率差检测器非常适用于提供时钟恢复电路的频率/锁相环。

公开(公告)号：US6016082A

公开(公告)日：2000-01-18

申请号：US23360

申请日：1998-02-13

申请人： Jose M. Cruz ,  Robert J. Bosnyak ,  Robert J. Drost

发明人： Jose M. Cruz ,  Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03B1/00 ,  H03B5/12 ,  H03L7/093 ,  H03L7/099 ,  H03L7/183 ,  H03B5/18

CPC分类号： H03L7/183 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1271 ,  H03L7/093 ,  H03L7/099 ,  H03B2201/0208

摘要： A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit. Continuously modifiable gigahertz frequency VCO circuit generates an output signal with a frequency that is dependent on the voltage on control voltage input line. The output signal from the continuously modifiable gigahertz frequency VCO is a differential current signal to a level shifter output circuit. The level shifter output circuit converts the current signal to a single-ended voltage that is supplied to an output driver. The output driver provides the output signal to a clock distribution network.

摘要翻译： 微处理器包括片上低相位噪声CMOS LC电容振荡器。 LC振荡器对电源波动相对不敏​​感。 此外，LC振荡器可以在足以支持正常全功率操作和微处理器的功率操作的减少的频率范围内操作。 LC振荡器使时钟抖动问题最小化，因此允许将微处理器工作频率扩展到甚至比以前更高的水平。 来自相位频率检测器的输出信号是LC振荡器的电平转换器和滤波器电路的频率控制输入线上的频率控制信号。 来自电平转换器和滤波器电路的输出信号是在可连续修改的千兆赫兹频率压控振荡器（VCO）电路的控制电压输入线上的滤波频率控制信号。 连续可修改的千兆赫兹频率VCO电路产生的输出信号的频率取决于控制电压输入线上的电压。 来自连续可修改的千兆赫兹频率VCO的输出信号是到电平移位器输出电路的差分电流信号。 电平移位器输出电路将电流信号转换为提供给输出驱动器的单端电压。 输出驱动器将输出信号提供给时钟分配网络。

公开(公告)号：US5920215A

公开(公告)日：1999-07-06

申请号：US885048

申请日：1997-06-30

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0896

摘要： In a charge pump the noise due to switching transients on the input pulse lines is kept to extremely low levels by translating input up/down pulses into small signal differential pulses which swing a differential pair of transistors by a small amount. This is done with level converters. The differential pair is kept in a saturation region, so that a large swing is not needed from the level converters and channel creation/destruction noise is avoided in addition to the noise reduction due to smaller swings. To avoid inherent offsets which might require a nonzero delta time width difference in the input pulses to produce a zero delta current, identical differential structures are used at the inputs for the two input pulse signals.

摘要翻译： 在电荷泵中，通过将输入上/下脉冲转换成将差分晶体管对摆动少量的小信号差分脉冲，将输入脉冲线上的切换瞬变引起的噪声保持在极低的水平。 这是用电平转换器完成的。 差分对保持在饱和区域，使得除了由于较小的摆动引起的噪声降低之外，电平转换器不需要大的摆幅并且避免了信道产生/破坏噪声。 为了避免可能需要输入脉冲中的非零增量时间宽度差产生零增量电流的固有偏移，在两个输入脉冲信号的输入端使用相同的差分结构。

公开(公告)号：US5850163A

公开(公告)日：1998-12-15

申请号：US828245

申请日：1997-03-31

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03B5/12 ,  H03H11/48 ,  H03L7/099 ,  H03B5/00

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1259 ,  H03B5/1271 ,  H03H11/48

摘要： An active inductor oscillator includes a tank circuit for generating a first differential signal, a common-mode inverting differential buffer for generating a second differential signal in response to the first differential signal, and an integrating circuit for generating a third differential signal in response to the second differential signal. The third differential signal is applied to the tank circuit, and lags the first differential signal. A differential transistor pair in the tank circuit provides active inductance in response to the third differential signal, and a cross-coupled transistor pair in the tank circuit provides negative resistance that amplifies the first differential signal in response to the first differential signal. Currents through the tank circuit, buffer, and integrating circuit are essentially identical to one another and move in unison with an externally applied reference current that controls the oscillation frequency. As a result, the oscillator can achieve a wide range of oscillation frequencies. The buffer adds 180 degrees of phase shift to the common-mode loop, thereby providing negative common-mode feedback that prevents lock-up. The tank circuit, buffer and integrating circuit use differential transistor pairs that reduce phase jitter due to external common-mode noise sources.

摘要翻译： 有源电感振荡器包括用于产生第一差分信号的振荡电路，用于响应于第一差分信号产生第二差分信号的共模反相差分缓冲器，以及用于响应于第一差分信号产生第三差分信号的积分电路 第二差分信号。 第三差分信号被施加到储能电路，并且滞后于第一差分信号。 储能电路中的差分晶体管对响应于第三差分信号提供有效电感，并且在谐振电路中的交叉耦合晶体管对提供响应于第一差分信号放大第一差分信号的负电阻。 通过储能电路，缓冲器和积分电路的电流基本上彼此相同，并与控制振荡频率的外部施加的参考电流一致地移动。 结果，振荡器可以实现宽范围的振荡频率。 缓冲器向共模环路增加180度的相移，从而提供防止锁定的负共模反馈。 储能电路，缓冲器和积分电路使用差分晶体管对，减少由于外部共模噪声源引起的相位抖动。

公开(公告)号：US06949406B2

公开(公告)日：2005-09-27

申请号：US10831576

申请日：2004-04-22

申请人： Robert J. Bosnyak ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L23/544 ,  H01L21/44

CPC分类号： H01L23/544 ,  H01L24/81 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2225/06527 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： One embodiment of the present invention provides a system that facilitates aligning a first semiconductor die with a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are arranged active face to active face. Note that the active face contains circuitry for communicating between semiconductor dies. The system starts by generating light on an active face of the first semiconductor die. The system then collimates the light within the active face of the first semiconductor die to form a first beam of light which is projected onto the second semiconductor die. Next, the system receives the first beam of light on an active face of the second semiconductor die and determines a position of the first beam of light on the active face of the second semiconductor die. Finally, the system determines an alignment of the second semiconductor die relative to the first semiconductor die based on the determined position of the first beam of light.

摘要翻译： 本发明的一个实施例提供一种便于将第一半导体管芯与第二半导体管芯对准的系统，其中第一半导体管芯和第二半导体管芯被配置为主动面朝向主动面。 注意，主动面包​​括用于在半导体管芯之间进行通信的电路。 系统通过在第一半导体管芯的有源面上产生光来开始。 然后，该系统使第一半导体管芯的有效面内的光准直，以形成投射到第二半导体管芯上的第一光束。 接下来，系统在第二半导体管芯的有效面上接收第一光束，并确定第一光束在第二半导体管芯的有效面上的位置。 最后，系统基于确定的第一光束的位置确定第二半导体管芯相对于第一半导体管芯的对准。

公开(公告)号：US06526552B1

公开(公告)日：2003-02-25

申请号：US09696451

申请日：2000-10-25

申请人： Robert J. Bosnyak ,  Jose M. Cruz ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  Jose M. Cruz ,  Robert J. Drost

IPC分类号： G06F945

CPC分类号： H04L25/0292 ,  H03K5/086

摘要： A clamping circuit which is connected to each long line, preferably adjacent the receiver. The clamping circuit biases the long line at the trigger threshold of the receiver. Thus, instead of amplifying the signal as a repeater will do, the present invention clamps the line to the threshold, thus allowing a faster response since the line doesn't have to be charged or discharged from a lower or higher level to the threshold. This thus speeds up the transition at the receiver without requiring a repeater or a keeper.

摘要翻译： 钳位电路，其连接到每个长线，优选地邻近接收器。 钳位电路在接收器的触发阈值处偏置长线。 因此，代替放大作为中继器的信号，本发明将线路钳位到阈值，从而允许更快的响应，因为线路不必从较低或更高的电平被充电或放电到阈值。 这样就加快了接收机的转换，而不需要中继器或保持器。

公开(公告)号：US06373304B1

公开(公告)日：2002-04-16

申请号：US08938932

申请日：1997-10-02

申请人： Robert J. Drost ,  Robert J. Bosnyak ,  Jose M. Cruz

发明人： Robert J. Drost ,  Robert J. Bosnyak ,  Jose M. Cruz

IPC分类号： H03K500

CPC分类号： H03L7/093

摘要： An improved loop filter contains an active device which maintains a phase lock loop's zero frequency to bandwidth ratio substantially constant with changes in the incoming frequency. It does this by maintaining filter resistance proportional to the inverse square root of the filter current, and without requiring duplicates of circuit elements. Constructed in this way a phase lock loop can be achieved which has a wide operating frequency range and low tracking jitter.

摘要翻译： 改进的环路滤波器包含一个有源器件，它通过输入频率的变化使锁相环的零频率与带宽比基本恒定。 它通过保持滤波器电阻与滤波器电流的反平方根成比例，并且不需要电路元件的重复来实现。 以这种方式构造，可以实现具有宽工作频率范围和低跟踪抖动的锁相环。