公开(公告)号：US20140059286A1

公开(公告)日：2014-02-27

申请号：US13989743

申请日：2011-10-06

申请人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

发明人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

IPC分类号： G06F13/16

CPC分类号： G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

摘要： Provided is a memory access device for a shared memory mechanism of main memory for a plurality of CPUs. The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

摘要翻译： 提供了一种用于多个CPU的主存储器的共享存储器机构的存储器访问装置。 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。

公开(公告)号：US20100177421A1

公开(公告)日：2010-07-15

申请号：US12351725

申请日：2009-01-09

申请人： Masayuki Demura ,  Glen Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

发明人： Masayuki Demura ,  Glen Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

IPC分类号： G11B5/09 ,  G11B15/00

CPC分类号： G11B20/1201 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1222 ,  G11B2220/90 ,  H03M13/271 ,  H03M13/2909

摘要： Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

摘要翻译： 方法，逻辑，设备和计算机程序产品写入数据，包括少于一个完整的数据集，到磁带。 从主机接收数据，发出不交错命令，并计算C1和C2 ECC。 然后形成Codeword Quad（CQ）集合。 将数据集的至少一个CQ集以非交错方式写入磁带，并且数据集信息表（DSIT）被写入紧跟在至少一个写入的CQ集之后的磁带上。 可以使用地址变换来取消交织。 编写CQ集可以包括将CQ集的多个连续实例写入磁带以保持ECC能力的有效性。

公开(公告)号：US09268721B2

公开(公告)日：2016-02-23

申请号：US13989743

申请日：2011-10-06

申请人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

发明人： Hisato Matsuo ,  Rika Nagahara ,  Kenji Ohtani

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/16

CPC分类号： G11C7/1048 ,  G06F13/1642 ,  G06F13/1647 ,  G06F13/1663 ,  G06F13/4234 ,  G11C7/1072

摘要： The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

摘要翻译： 本发明包括使用存储器作为主存储器的多个CPU，使用存储器作为缓冲器的另一功能块，控制从多个CPU到存储器的访问传输的CPU接口，以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中，CPU接口使得来自多个CPU的访问请求等待，并且接收并存储每个访问的地址，数据传输模式和数据大小，向DRAM控制器通知访问请求，然后在接收到 访问请求根据授权信号向DRAM控制器发送信息，于是DRAM控制器接收授权信号，并且基于访问仲裁，指定已经被授权传输的CPU，以便将授权信号发送到 CPU接口。

公开(公告)号：US20110125946A1

公开(公告)日：2011-05-26

申请号：US12916668

申请日：2010-11-01

申请人： Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

发明人： Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

IPC分类号： G06F13/18 ,  G06F12/06

CPC分类号： G06F13/161 ,  G06F13/1673 ,  Y02D10/14

摘要： Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

摘要翻译： 存储器访问仲裁允许共享存储器既用作处理器的存储器又用作数据流的缓冲器，包括仲裁器单元，其顺序地对存储器的访问请求进行分配，并在一个循环周期中传送数据块 根据数据传输所需的带宽，设置传输块的优先级，使得通过传输块的交替传送来满足数据传输所需的带宽，并且执行对处理器的访问，其具有为 在一个循环周期中从处理器到存储器的访问时间，使得来自具有最高优先级并且具有预定传送长度的处理器的访问对传输块之间的预定间隔中的数据流传输的带宽的影响较小。

公开(公告)号：US07965462B2

公开(公告)日：2011-06-21

申请号：US12351725

申请日：2009-01-09

申请人： Masayuki Demura ,  Glen A. Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

发明人： Masayuki Demura ,  Glen A. Jaquette ,  Hisato Matsuo ,  Keisuke Tanaka

IPC分类号： G11B20/16

CPC分类号： G11B20/1201 ,  G11B20/18 ,  G11B20/1866 ,  G11B2020/1222 ,  G11B2220/90 ,  H03M13/271 ,  H03M13/2909

摘要： Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

摘要翻译： 方法，逻辑，设备和计算机程序产品写入数据，包括少于一个完整的数据集，到磁带。 从主机接收数据，发出不交错命令，并计算C1和C2 ECC。 然后形成Codeword Quad（CQ）集合。 将数据集的至少一个CQ集以非交错方式写入磁带，并且数据集信息表（DSIT）被写入紧跟在至少一个写入的CQ集之后的磁带上。 可以使用地址变换来取消交织。 编写CQ集可以包括将CQ集的多个连续实例写入磁带以保持ECC能力的有效性。

公开(公告)号：US08412891B2

公开(公告)日：2013-04-02

申请号：US12916668

申请日：2010-11-01

申请人： Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

发明人： Masayuki Demura ,  Hisato Matsuo ,  Keisuke Tanaka

IPC分类号： G06F12/12 ,  G06F13/18 ,  G06F13/34

CPC分类号： G06F13/161 ,  G06F13/1673 ,  Y02D10/14

摘要： Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

摘要翻译： 存储器访问仲裁允许共享存储器既用作处理器的存储器又用作数据流的缓冲器，包括仲裁器单元，其顺序地对存储器的访问请求进行分配，并在一个循环周期中传送数据块 根据数据传输所需的带宽，设置传输块的优先级，使得通过传输块的交替传送来满足数据传输所需的带宽，并且执行对处理器的访问，其具有为 在一个循环周期中从处理器到存储器的访问时间，使得来自具有最高优先级并且具有预定传送长度的处理器的访问对传输块之间的预定间隔中的数据流传输的带宽的影响较小。

公开(公告)号：US20100172047A1

公开(公告)日：2010-07-08

申请号：US12350108

申请日：2009-01-07

申请人： Evangelos S. Eleftheriou ,  Robert Allen Hutchins ,  Hisato Matsuo ,  Sedat Oelcer

发明人： Evangelos S. Eleftheriou ,  Robert Allen Hutchins ,  Hisato Matsuo ,  Sedat Oelcer

IPC分类号： G11B20/10 ,  G11B5/78

CPC分类号： G11B20/10009 ,  G11B20/10055 ,  G11B20/10175 ,  G11B20/10222 ,  G11B2220/90

摘要： A system in one embodiment includes multiple analog inputs for receiving readback signals, an analog to digital converter coupled to each of the analog inputs for converting the readback signals to digital signals, a buffer coupled to outputs of the analog to digital converters for at least temporarily storing the digital signals, and a digital processing section also coupled to outputs of the analog to digital converters for processing the digital signals for reconstructing data therefrom. A method in one embodiment includes receiving multiple channels of analog readback signals from a magnetic head, converting the analog signals in each channel to digital signals, buffering the digital signals, and outputting the buffered digital signals. A method in another embodiment includes receiving a readback waveform from a magnetic storage device, reducing a frequency offset of the readback waveform, and generating a synchronized, oversampled waveform from the readback waveform.

摘要翻译： 一个实施例中的系统包括用于接收回读信号的多个模拟输入，耦合到每个模拟输入的模数转换器，用于将回读信号转换成数字信号;耦合到模数转换器的输出的缓冲器，用于至少暂时地 存储数字信号，以及数字处理部分，其耦合到模数转换器的输出端，用于处理数字信号以从其重构数据。 一个实施例中的方法包括从磁头接收多个通道的模拟回读信号，将每个通道中的模拟信号转换成数字信号，缓冲数字信号，并输出缓冲的数字信号。 另一实施例中的方法包括从磁存储设备接收回读波形，减少回读波形的频率偏移，以及从回读波形生成同步的过采样波形。

公开(公告)号：US20080209420A1

公开(公告)日：2008-08-28

申请号：US12039412

申请日：2008-02-28

申请人： Hisato Matsuo

发明人： Hisato Matsuo

IPC分类号： G06F9/46

CPC分类号： G06F3/0656 ,  G06F3/0613 ,  G06F3/0682

摘要： Provided is a technology capable of managing the processing status of hardware blocks by a less number of registers. A processing system includes a buffer composed of a plurality of segments which store data, which is to be input to the processing system, in transactions in the order of inputting, respectively; a plurality of processing units which perform a series of processes in a given order for the data; a plurality of first tables corresponding to the plurality of processing units, respectively, the first tables each storing beginning information which indicates a beginning segment among a plurality of segments at continuous addresses completed in the process by the corresponding processing unit, end information which indicates an end segment among them, and existence information which indicates the presence or absence of segments completed in the process by the corresponding processing unit; and a management unit which manages a data transfer between the buffer and the plurality of processing units so that the series of processes are performed in a given order on the basis of the processing status of the series of processes retained in the plurality of first tables.

摘要翻译： 提供了能够通过较少数量的寄存器来管理硬件块的处理状态的技术。 一种处理系统，包括分别以输入顺序存储要输入到处理系统的数据的多个段的缓冲器; 多个处理单元，以给定顺序执行数据的一系列处理; 分别对应于多个处理单元的多个第一表，每个存储开始信息的第一表，其中表示在相应处理单元处理完成的连续地址的多个段中的起始段，表示一个 以及存在信息，其指示由对应的处理单元在该处理中完成的段的存在或不存在; 以及管理单元，其管理所述缓冲器和所述多个处理单元之间的数据传送，使得根据保持在所述多个第一表中的所述一系列处理的处理状态，以给定的顺序执行所述一系列处理。

公开(公告)号：US08209693B2

公开(公告)日：2012-06-26

申请号：US12039412

申请日：2008-02-28

申请人： Hisato Matsuo

发明人： Hisato Matsuo

IPC分类号： G06F9/46

CPC分类号： G06F3/0656 ,  G06F3/0613 ,  G06F3/0682

摘要： Provided is a technology capable of managing the processing status of hardware blocks by a less number of registers. A processing system includes a buffer composed of a plurality of segments which store data, which is to be input to the processing system, in transactions in the order of inputting, respectively; a plurality of processing units which perform a series of processes in a given order for the data; a plurality of first tables corresponding to the plurality of processing units, respectively, the first tables each storing beginning information which indicates a beginning segment among a plurality of segments at continuous addresses completed in the process by the corresponding processing unit, end information which indicates an end segment among them, and existence information which indicates the presence or absence of segments completed in the process by the corresponding processing unit; and a management unit which manages a data transfer between the buffer and the plurality of processing units so that the series of processes are performed in a given order on the basis of the processing status of the series of processes retained in the plurality of first tables.

摘要翻译： 提供了能够通过较少数量的寄存器来管理硬件块的处理状态的技术。 一种处理系统，包括分别以输入顺序存储要输入到处理系统的数据的多个段的缓冲器; 多个处理单元，以给定顺序执行数据的一系列处理; 分别对应于多个处理单元的多个第一表，每个存储开始信息的第一表，其中表示在相应处理单元处理完成的连续地址的多个段中的起始段，表示一个 以及存在信息，其指示由对应的处理单元在该处理中完成的段的存在或不存在; 以及管理单元，其管理所述缓冲器和所述多个处理单元之间的数据传送，使得根据保持在所述多个第一表中的所述一系列处理的处理状态，以给定的顺序执行所述一系列处理。

公开(公告)号：US20080320361A1

公开(公告)日：2008-12-25

申请号：US11721446

申请日：2005-12-21

申请人： Junichi Fukuda ,  Hisato Matsuo

发明人： Junichi Fukuda ,  Hisato Matsuo

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11B20/1803 ,  G11B20/1833 ,  G11B2020/10629 ,  G11B2020/1823 ,  G11B2020/1853 ,  G11B2220/90

摘要： A method for transferring corrected data to an external buffer within a tape drive is disclosed. After the receipt of data from a data recording medium, the data are stored in an external buffer. The data are then transferred from the external buffer to an error correction code (ECC) device. Any error in the data within the ECC device are corrected. The corrected data are subsequently divided into multiple sub-units, and a transfer flag is added to each of the sub-units having corrected data. Only the sub-units having corrected data are transferred from the ECC device back to the external buffer.

摘要翻译： 公开了一种用于将校正数据传送到磁带机内的外部缓冲器的方法。 在从数据记录介质接收数据之后，将数据存储在外部缓冲器中。 然后将数据从外部缓冲器传送到纠错码（ECC）设备。 纠正ECC设备内的数据错误。 校正后的数据随后被分成多个子单元，并将传送标志加到具有校正数据的每个子单元中。 只有具有校正数据的子单元才从ECC设备传送回外部缓冲器。