公开(公告)号：US06737675B2

公开(公告)日：2004-05-18

申请号：US10180046

申请日：2002-06-27

申请人： Kedar Patel ,  Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker

发明人： Kedar Patel ,  Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker

IPC分类号： H01L2976

CPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052

摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

摘要翻译： 半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。 单片三维阵列包含多个这样的装置。 阵列的不同级别的晶体管优选地具有不同的取向。

公开(公告)号：US20050044459A1

公开(公告)日：2005-02-24

申请号：US10961501

申请日：2004-10-08

申请人： Roy Scheuerlein ,  Mark Johnson ,  Derek Bosch ,  Alper Ilkbahar ,  J. Tringali

发明人： Roy Scheuerlein ,  Mark Johnson ,  Derek Bosch ,  Alper Ilkbahar ,  J. Tringali

IPC分类号： G11C7/10 ,  G11C7/24 ,  G11C29/00 ,  G11C29/44

CPC分类号： G11C29/76 ,  G11C7/1006 ,  G11C7/24 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/78

摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

公开(公告)号：US20060221702A1

公开(公告)日：2006-10-05

申请号：US11146952

申请日：2005-06-07

申请人： Roy Scheuerlein ,  Christopher Petti ,  Luca Fasoli

发明人： Roy Scheuerlein ,  Christopher Petti ,  Luca Fasoli

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14

摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.

摘要翻译： 公开了一种用于非二进制组的存储器线驱动器的解码电路。 在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。 在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一 。 控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。 本文所述的概念可以单独使用或组合使用。

公开(公告)号：US20050122779A1

公开(公告)日：2005-06-09

申请号：US10729843

申请日：2003-12-05

申请人： Luca Fasoli ,  Roy Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew Walker

发明人： Luca Fasoli ,  Roy Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew Walker

IPC分类号： G11C16/04

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括至少一个存储器单元平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，以及包括每个的串联选择器件的NAND串 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

公开(公告)号：US20070217263A1

公开(公告)日：2007-09-20

申请号：US11751567

申请日：2007-05-21

申请人： Luca Fasoli ,  Roy Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew Walker

发明人： Luca Fasoli ,  Roy Scheuerlein ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Maitreyee Mahajani ,  Andrew Walker

IPC分类号： G11C16/04

CPC分类号： G11C16/04

摘要： An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

摘要翻译： 示例性NAND串存储器阵列包括存储器单元的至少一个平面，所述存储器单元包括薄膜可修改的电导开关器件，并且哪些单元被布置在多个串联的NAND串中，所述NAND串包括每个的串联选择器件 结束。 另一示例性的NAND串存储器阵列包括在相同存储器块内的多于四个相邻的NAND串的组，每组相关联的不同于该组的另一个NAND串的相应全局位线。 另一示例性的NAND串存储器阵列包括与它们各自的全局位线相同的音调的NAND串。

公开(公告)号：US20060221752A1

公开(公告)日：2006-10-05

申请号：US11095415

申请日：2005-03-31

申请人： Luca Fasoli ,  Roy Scheuerlein

发明人： Luca Fasoli ,  Roy Scheuerlein

IPC分类号： G11C8/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C7/18 ,  G11C29/808 ,  H01L27/101 ,  H01L27/105 ,  Y10T29/49002

摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

摘要翻译： 具有三维存储器阵列的集成电路提供给定数量的存储器平面，但是可以通过省略与所省略的存储器平面相关联的掩模和处理步骤来替代地制造更少数量的存储器层，而不改变任何 用于其他存储器平面或其余器件的其他制造掩模，并且不需要对阵列的读取或读取/写入路径进行路由或其他配置更改。 用于选择性地启用某些层选择器电路的控制电路是可配置的，并且层选择器电路被适当地布置，以将实现的存储器层上的相应阵列线耦合到每个相应的I / O总线，而与所实现的存储器平面的数量无关。

公开(公告)号：US20060221728A1

公开(公告)日：2006-10-05

申请号：US11095907

申请日：2005-03-31

申请人： Luca Fasoli ,  Roy Scheuerlein

发明人： Luca Fasoli ,  Roy Scheuerlein

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/76 ,  G11C29/804 ,  G11C29/816

摘要： An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.

公开(公告)号：US20060146608A1

公开(公告)日：2006-07-06

申请号：US11026492

申请日：2004-12-30

申请人： Luca Fasoli ,  Roy Scheuerlein

发明人： Luca Fasoli ,  Roy Scheuerlein

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/005 ,  H01L27/11524 ,  H01L27/11551

摘要： A monolithic integrated circuit includes a memory array having first and second groups of NAND strings, each NAND string comprising at least two series-connected devices and coupled at one end to an associated global array line. NAND strings of the first and second groups differ in at least one physical characteristic, such as the number of series-connected devices forming the NAND string, but both groups are disposed in a region of the memory array traversed by a plurality of global array lines. The memory array may include a three-dimensional memory array having more than one memory plane. Some of the NAND strings of the first group may be disposed on one memory plane, and some of the NAND strings of the second group may be disposed on another memory plane. In some cases, NAND strings of both groups may share global array lines.

摘要翻译： 单片集成电路包括具有第一和第二组NAND串的存储器阵列，每个NAND串包括至少两个串联连接的器件，并在一端耦合到相关联的全局阵列线。 第一组和第二组的NAND串在至少一个物理特性方面不同，例如形成NAND串的串联连接器件的数量，但两组都设置在由多个全局阵列线穿过的存储器阵列的区域中 。 存储器阵列可以包括具有多于一个存储器平面的三维存储器阵列。 第一组的一些NAND串可以被布置在一个存储器平面上，并且第二组的一些NAND串可以被布置在另一个存储器平面上。 在某些情况下，两组的NAND串可能共享全局阵列线。

公开(公告)号：US20060145193A1

公开(公告)日：2006-07-06

申请号：US11026493

申请日：2004-12-30

申请人： Kenneth So ,  Luca Fasoli ,  Roy Scheuerlein

发明人： Kenneth So ,  Luca Fasoli ,  Roy Scheuerlein

IPC分类号： H01L27/10 ,  G11C5/06

CPC分类号： G11C8/10

摘要： In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.

摘要翻译： 在本发明的一个实施例中，集成电路包括存储器阵列，该存储器阵列具有遍及存储器阵列的第一多条解码线和一对双模式解码器，每个解码器耦合到多条解码线中的每条解码线， 解码线，例如在其相对端。 两个解码器电路都接收类似的地址信息。 通常两个解码器电路都以正向解码模式工作，以对地址信息进行解码并驱动所选择的解码行之一。 在测试模式期间，一个解码器以反向解码模式使能，而另一个解码器保持在正向解码模式，以验证解码器之间解码线路的正确解码操作和完整性。

公开(公告)号：US20060133125A1

公开(公告)日：2006-06-22

申请号：US11015440

申请日：2004-12-17

申请人： Kenneth So ,  Luca Fasoli ,  Roy Scheuerlein

发明人： Kenneth So ,  Luca Fasoli ,  Roy Scheuerlein

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677

摘要： An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.

摘要翻译： 公开了一种包括多个字线和字线驱动器，多个位线和位线驱动器以及耦合在各个字线和位线之间的多个存储器单元的装置。 该装置还包括电路，用于基于相对于字线驱动器和位线驱动器中的一个或两者的存储单元的位置来选择写入和/或读取条件以应用于存储器单元。 该装置还可以包括电路，其可操作以基于相对于字线和/或位线驱动器的存储器单元位置来并行地选择要编程的多个存储器单元。