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229 条记录 (耗时 0.031 秒)

    Compute unit with an internal bit FIFO circuit
    11.
    发明授权
    Compute unit with an internal bit FIFO circuit 有权
    具有内部位FIFO电路的计算单元

    公开(公告)号：US07882284B2

    公开(公告)日：2011-02-01

    申请号：US11728358

    申请日：2007-03-26

    申请人： James Wilson ,  Yosef Stein ,  Joshua A. Kablotsky

    发明人： James Wilson ,  Yosef Stein ,  Joshua A. Kablotsky

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G11C7/10

    CPC分类号： G06F5/10 ,  G06F5/00 ,  G06F5/065 ,  G06F5/14 ,  G06F9/30018 ,  G06F9/3824 ,  G06F2205/126

    摘要： A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

    摘要翻译： 具有内部位FIFO电路的计算单元包括至少一个数据寄存器，查找表，包括用于将查找表的一部分配置为位FIFO电路的FIFO基址，长度和读/写模式字段的配置寄存器，以及 读/写指针寄存器响应于具有查找表识别字段，位字段长度和寄存器提取/存储字段的指令，用于在FIFO电路和数据寄存器之间的单个周期中选择性地传送具有指定长度的位字段。

    Instruction-Based Parallel Median Filtering
    12.
    发明申请
    Instruction-Based Parallel Median Filtering 有权
    基于指令的并行中值滤波

    公开(公告)号：US20090327378A1

    公开(公告)日：2009-12-31

    申请号：US12554500

    申请日：2009-09-04

    申请人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Gregory M. Yukna

    发明人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Gregory M. Yukna

    IPC分类号： G06F7/38 ,  G06F17/10

    CPC分类号： G06F7/22 ,  G06F7/544 ,  G06F17/18 ,  H03H17/0263 ,  H03H2017/0298

    摘要： An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.

    摘要翻译： 基于指令的并行中值滤波处理器和方法将每组输入的输入并行分成更大和更小的值; 根据输入的最小值，最大值和中值滤波器值进行排序; 处理这些值之一并将处理的值提供为输入; 并且向所述处理步骤应用用于提供所述值中的一个的指令，以及用于使得能够指示所述最大值，最小中值滤波器值中的至少一个的至少一个其他指令。

    METHODS OF GENERATING CHIMERIC ADENOVIRUSES AND USES FOR SUCH CHIMERIC ADENOVIRUSES
    15.
    发明申请
    METHODS OF GENERATING CHIMERIC ADENOVIRUSES AND USES FOR SUCH CHIMERIC ADENOVIRUSES 有权
    产生阴性腺瘤病毒的方法和用于这些重型腺病毒的方法

    公开(公告)号：US20070231303A1

    公开(公告)日：2007-10-04

    申请号：US10465302

    申请日：2003-06-20

    申请人： Soumitra Roy ,  James Wilson

    发明人： Soumitra Roy ,  James Wilson

    IPC分类号： A61K48/00 ,  C07H21/02 ,  C12N15/861 ,  C12N5/06 ,  C12N7/00 ,  C07K14/075

    CPC分类号： C12N15/86 ,  C07K14/005 ,  C12N7/00 ,  C12N2710/10343 ,  C12N2710/10344 ,  C12N2810/6018

    摘要： A method for providing an adenovirus from a serotype which does not grow efficiently in a desired cell line with the ability to grow in that cell line is described. The method involves replacing the left and right termini of the adenovirus with the corresponding termini from an adenovirus which grow efficiently in the desired cell line. At a minimum, the left terminus spans the 5′ inverted terminal repeat, the left terminus spans the E4 region and the 3′ inverted terminal repeat. The resulting chimeric adenovirus contains the internal regions spanning the genes encoding the penton, hexon and fiber from the serotype which does not grow efficiently in the desired cell. Also provided are vectors constructed from novel simian adenovirus sequences and proteins, host cells containing same, and uses thereof.

    摘要翻译： 描述了从在该细胞系中具有生长能力的所需细胞系中不能有效生长的血清型提供腺病毒的方法。 该方法包括用在期望的细胞系中有效生长的腺病毒的相应末端替换腺病毒的左侧和右侧末端。 至少，左终点跨越5'反向末端重复，左侧末端跨越E4区域，3'反向末端重复。 所得到的嵌合腺病毒包含跨越编码来自血清型的五邻体，六邻体和纤维的基因的内部区域，其不能在期望的细胞中有效生长。 还提供了由新型猿猴腺病毒序列和蛋白构成的载体，含有其的宿主细胞及其用途。

    DUAL OPERATIONAL MODE CML LATCH
    17.
    发明申请
    DUAL OPERATIONAL MODE CML LATCH 失效
    双操作模式CML锁

    公开(公告)号：US20070200605A1

    公开(公告)日：2007-08-30

    申请号：US11307923

    申请日：2006-02-28

    申请人： Joseph Marsh ,  Joseph Natonio ,  James Wilson

    发明人： Joseph Marsh ,  Joseph Natonio ,  James Wilson

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356043

    摘要： A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

    摘要翻译： 提供了一种双用途电流模式逻辑（“CML”）锁存电路，其包括可操作以接收至少一对差分输入数据信号和至少一个时钟信号的CML锁存器。 CML锁存器可操作以根据输入差分数据信号对的状态产生至少一个输出信号。 模式控制装置可操作以接收模式控制信号以将CML锁存器作为缓冲器或锁存器操作。 以这种方式，当模式控制信号无效时，CML锁存器产生并以由至少一个时钟信号确定的定时锁存输出信号，并且当模式控制信号有效时，CML锁存器产生输出信号，使得 每当差分输入数据信号对的状态改变时，输出信号就会改变。

    Monitoring system
    19.
    发明申请
    Monitoring system 审中-公开
    监视系统

    公开(公告)号：US20070091818A1

    公开(公告)日：2007-04-26

    申请号：US11586405

    申请日：2006-10-25

    申请人： Kevin Kroupa ,  James Wilson ,  Christopher Scholz

    发明人： Kevin Kroupa ,  James Wilson ,  Christopher Scholz

    IPC分类号： H04J1/16

    CPC分类号： H04L41/0681 ,  G06F19/3418 ,  G16H40/20 ,  H04L41/0226 ,  H04L43/00 ,  H04L43/16 ,  H04L43/50

    摘要： A monitoring system including a computer system; a data converter connected to the computer system through a cable; one or more panels each connected to the data converter through one or more data lines; the one or more panels obtaining data by measuring a measurable component of a near or remote system. The computer system monitors the one or more panels to determine when an alarm condition exists and to provide data from the one or more panels.

    摘要翻译： 一种包括计算机系统的监控系统; 数据转换器，通过电缆连接到计算机系统; 一个或多个面板通过一个或多个数据线连接到数据转换器; 所述一个或多个面板通过测量近或远程系统的可测量分量来获得数据。 计算机系统监视一个或多个面板以确定何时存在警报状况并且从一个或多个面板提供数据。