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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220139897A1

    公开(公告)日：2022-05-05

    申请号：US17577647

    申请日：2022-01-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： CHANHO KIM ,  JOO-YONG PARK ,  DAESEOK BYEON

    IPC: H01L25/18 ,  H01L23/00

    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
    13.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210074716A1

    公开(公告)日：2021-03-11

    申请号：US16931500

    申请日：2020-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： BONGSOON LIM ,  DAESEOK BYEON

    IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11565 ,  G11C8/14 ,  G11C7/18 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11556

    Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE AND VEHICLE-BASED SYSTEM INCLUDING MEMORY SYSTEM
    15.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE AND VEHICLE-BASED SYSTEM INCLUDING MEMORY SYSTEM 有权

    公开(公告)号：US20210132816A1

    公开(公告)日：2021-05-06

    申请号：US17027978

    申请日：2020-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNGMIN JO ,  DAESEOK BYEON ,  TONGSUNG KIM

    IPC: G06F3/06 ,  G06F12/02 ,  G06N3/08

    Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O pins connected to the second channel group, wherein the memory area includes at least one memory chip, wherein the at least one memory chip includes a first chip having a first metal pad and a cell region and a second chip having a second metal pad and a peripheral circuit region, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

    NON-VOLATILE MEMORY DEVICE
    17.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210065799A1

    公开(公告)日：2021-03-04

    申请号：US16944312

    申请日：2020-07-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANHO KIM ,  KYUNGHWA YUN ,  DAESEOK BYEON

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
    19.
    发明申请
    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT 有权

    公开(公告)号：US20220122673A1

    公开(公告)日：2022-04-21

    申请号：US17227501

    申请日：2021-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEUNGYEON KIM ,  DAESEOK BYEON ,  PANSUK KWAK ,  HONGSOO JEON

    IPC: G11C16/24 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C16/26

    Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    20.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210066282A1

    公开(公告)日：2021-03-04

    申请号：US17002149

    申请日：2020-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： CHANHO KIM ,  JOO-YONG PARK ,  DAESEOK BYEON

    IPC: H01L25/18 ,  H01L23/00

    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

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