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    SEMICONDUCTOR PACKAGE
    12.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220375829A1

    公开(公告)日：2022-11-24

    申请号：US17533606

    申请日：2021-11-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonjeong Hwang ,  Minjung Kim ,  Dongkyu Kim ,  Taewon Yoo

    IPC: H01L23/49 ,  H01L23/498 ,  H01L23/31

    Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

    Semiconductor package including a dummy pattern
    13.
    发明授权
    Semiconductor package including a dummy pattern 有权

    公开(公告)号：US12211777B2

    公开(公告)日：2025-01-28

    申请号：US17731416

    申请日：2022-04-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minjung Kim ,  Dongkyu Kim ,  Jongyoun Kim ,  Hyeonjeong Hwang

    IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

    Abstract: A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

    SEMICONDUCTOR PACKAGE
    14.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240113001A1

    公开(公告)日：2024-04-04

    申请号：US18212939

    申请日：2023-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyounglim SUK ,  Jihwang Kim ,  Suchang Lee ,  Hyeonjeong Hwang

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/64 ,  H01L25/065

    CPC classification number: H01L23/49822 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16227

    Abstract: A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

    PACKAGED INTEGRATED CIRCUIT HAVING ENHANCED ELECTRICAL INTERCONNECTS THEREIN
    16.
    发明公开
    PACKAGED INTEGRATED CIRCUIT HAVING ENHANCED ELECTRICAL INTERCONNECTS THEREIN 审中-公开

    公开(公告)号：US20240071894A1

    公开(公告)日：2024-02-29

    申请号：US18335336

    申请日：2023-06-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeonjeong Hwang ,  Dongkyu Kim ,  Kyounglim Suk ,  Hyeonseok Lee

    IPC: H01L23/498

    CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

    Abstract: A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.

    IMAGE SENSOR PACKAGE INCLUDING GLASS SUBSTRATE
    18.
    发明申请
    IMAGE SENSOR PACKAGE INCLUDING GLASS SUBSTRATE 有权

    公开(公告)号：US20220165778A1

    公开(公告)日：2022-05-26

    申请号：US17363931

    申请日：2021-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minjung Kim ,  Dongkyu Kim ,  Kyounglim Suk ,  Jaegwon Jang ,  Hyeonjeong Hwang

    IPC: H01L27/146

    Abstract: An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 μm to 1 mm. The second distance is equal to or less than 0.1 mm.

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