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    Semiconductor package
    11.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11837553B2

    公开(公告)日：2023-12-05

    申请号：US17405696

    申请日：2021-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/538 ,  H01L23/544 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

    CPC classification number: H01L23/544 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517

    Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

    SEMICONDUCTOR PACKAGE
    12.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220165634A1

    公开(公告)日：2022-05-26

    申请号：US17405696

    申请日：2021-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

    SEMICONDUCTOR PACKAGE
    13.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250149520A1

    公开(公告)日：2025-05-08

    申请号：US18780675

    申请日：2024-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junghoon Kang ,  Daegon Kim

    IPC: H01L25/18 ,  G02B6/12 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L27/144

    Abstract: A semiconductor package including a package substrate, a plurality of chiplets located on the package substrate, the plurality of chiplets including a photonics chip and a semiconductor chip located on the photonics chip, and a plurality of photonics bridge chips located on the package substrate. The plurality of chiplets are spaced apart from each other in a horizontal direction, and each of the plurality of photonics bridge chips is located between the plurality of chiplets.

    SEMICONDUCTOR PACKAGE
    14.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250149516A1

    公开(公告)日：2025-05-08

    申请号：US18780730

    申请日：2024-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junghoon Kang ,  Daegon Kim

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/498 ,  H01L23/538 ,  H01L27/144 ,  H10B80/00

    Abstract: A semiconductor package including a package substrate, a plurality of photonics bridge chips located on the package substrate, a molding layer located on the package substrate, surrounding the plurality of photonics bridge chips, and including a plurality of via electrodes, and a plurality of chiplets located on the molding layer and the plurality of photonics bridge chips, the chiplets each including a photonics chip and a semiconductor chip located on the photonics chip, wherein the plurality of chiplets are spaced apart from each other in a horizontal direction, and at least two chiplets adjacent to each other from among the plurality of chiplets overlap one photonics bridge chip from among the plurality of photonics bridge chips in a vertical direction.

    Method of manufacturing semiconductor package, and semiconductor package
    15.
    发明授权
    Method of manufacturing semiconductor package, and semiconductor package 有权

    公开(公告)号：US12230580B2

    公开(公告)日：2025-02-18

    申请号：US17695478

    申请日：2022-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

    Abstract: A method includes attaching a first anisotropic conductive film including first conductive particles to a front surface of a substrate structure; compressing a first redistribution structure on the front surface of the substrate structure such that a first redistribution conductor of the first redistribution structure that is exposed is electrically connected by the first conductive particles to a connection terminal or a vertical connection conductor that is exposed from the substrate structure, attaching a second anisotropic conductive film including second conductive particles to a rear surface of the substrate structure; and compressing a second redistribution structure on the rear surface of the substrate structure such that a second redistribution conductor of the second redistribution structure that is exposed is electrically connected by the second conductive particles to the vertical connection conductor.

    SEMICONDUCTOR PACKAGE
    17.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240055364A1

    公开(公告)日：2024-02-15

    申请号：US18496372

    申请日：2023-10-27

    Applicant: Samsung Electronics Co.,Ltd.

    Inventor： Junghoon Kang

    IPC: H01L23/544 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

    CPC classification number: H01L23/544 ,  H01L23/3121 ,  H01L23/5386 ,  H01L23/5384 ,  H01L25/0657 ,  H01L24/16 ,  H01L2225/06517 ,  H01L2224/16225

    Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

    SEMICONDUCTOR PACKAGE WITH PHOTONICS CHIP
    18.
    发明申请
    SEMICONDUCTOR PACKAGE WITH PHOTONICS CHIP 有权

    公开(公告)号：US20250116810A1

    公开(公告)日：2025-04-10

    申请号：US18887727

    申请日：2024-09-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daegon Kim ,  Junghoon Kang

    IPC: G02B6/12 ,  G02B6/13 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

    Abstract: A semiconductor package includes an interposer including an interposer optical waveguide, and a plurality of chiplets coupled onto the interposer and each including a semiconductor chip and a photonics chip electrically coupled to the semiconductor chip, wherein the photonics chip includes a photonic integrated circuit configured to input or output an optical signal, and an optical waveguide optically coupled to the interposer optical waveguide.

    Semiconductor package having pad with regular and irregular depressions and protrusions and method of manufacturing the same
    19.
    发明授权
    Semiconductor package having pad with regular and irregular depressions and protrusions and method of manufacturing the same 有权

    公开(公告)号：US11929315B2

    公开(公告)日：2024-03-12

    申请号：US17527414

    申请日：2021-11-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

    CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16227

    Abstract: A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.

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