公开(公告)号：US20230163213A1

公开(公告)日：2023-05-25

申请号：US17843970

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGGIL LEE ,  SEOKHOON KIM ,  SUNGMIN KIM ,  JUNGTAEK KIM ,  PANKWI PARK ,  DONGSUK SHIN ,  NAMKYU CHO ,  RYONG HA ,  YANG XU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L29/7848 ,  H01L29/42312 ,  H01L29/49 ,  H01L29/41791 ,  H01L21/02233 ,  H01L21/02532

Abstract: Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.

公开(公告)号：US20230111579A1

公开(公告)日：2023-04-13

申请号：US17815187

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： RYONG HA ,  SEOKHOON KIM ,  DOHYUN GO ,  JUNGTAEK KIM ,  MOON SEUNG YANG ,  SANGIL LEE ,  SEOJIN JEONG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/40

Abstract: A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.

公开(公告)号：US20210367036A1

公开(公告)日：2021-11-25

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINBUM KIM ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  ILGYOU SHIN ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.