公开(公告)号：US20210336007A1

公开(公告)日：2021-10-28

申请号：US17371858

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGGIL LEE ,  NAMKYU CHO ,  SEOKHOON KIM ,  KANG HUN MOON ,  HYUN-KWAN YU ,  SIHYUNG LEE

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

公开(公告)号：US20150206955A1

公开(公告)日：2015-07-23

申请号：US14498996

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Seong Hoon JEONG ,  JEON IL LEE ,  SEOKHOON KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Yu-Jin PYO

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract translation: 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。

公开(公告)号：US20230017277A1

公开(公告)日：2023-01-19

申请号：US17935561

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  SEOKHOON KIM ,  KWANHEUM LEE ,  CHOEUN LEE ,  SUJIN JUNG

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

公开(公告)号：US20210043730A1

公开(公告)日：2021-02-11

申请号：US16789498

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGGIL LEE ,  NAMKYU CHO ,  SEOKHOON KIM ,  KANG HUN MOON ,  HYUN-KWAN YU ,  SIHYUNG LEE

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

公开(公告)号：US20150287711A1

公开(公告)日：2015-10-08

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHOON KIM ,  BONYOUNG KOO ,  JinBum KIM ,  CHUL KIM ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Sujin JUNG

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。

公开(公告)号：US20240387717A1

公开(公告)日：2024-11-21

申请号：US18513853

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOHOON BYEON ,  SEOKHOON KIM ,  YUYEONG JO ,  PANKWI PARK ,  SUNGKEUN LIM

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: a substrate including an active pattern; a first channel structure overlapping the active pattern; a gate electrode including an electrode portion between the active pattern and the first channel structure; a semiconductor layer contacting the first channel structure; and a source/drain pattern contacting the first channel structure, wherein the first channel structure includes: a first upper channel layer; a first lower channel layer; and a first intervening channel layer disposed between the first upper channel layer and the first lower channel layer, wherein the semiconductor layer contacts a sidewall of the first upper channel layer, a sidewall of the first lower channel layer, and a sidewall of the first intervening channel layer, and wherein the semiconductor layer and the first intervening channel layer include a semiconductor material that is different from a semiconductor material of the first upper channel layer and the first lower channel layer.

公开(公告)号：US20240162293A1

公开(公告)日：2024-05-16

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  Ilgyou Shin ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20220344469A1

公开(公告)日：2022-10-27

申请号：US17862453

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINBUM KIM ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  ILGYOU SHIN ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20180122922A1

公开(公告)日：2018-05-03

申请号：US15800242

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHOON KIM ,  WOO BIN SONG ,  SUNJUNG KIM ,  JinBum KIM ,  SANGMOON LEE ,  SEUNG HUN LEE ,  DONGSUK SHIN

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L23/31

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42364 ,  H01L29/785 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device. The semiconductor device comprises a fin structure on a substrate, device isolation patterns provided on the substrate and disposed on opposite sides of the fin structure, a gate electrode running across the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and a capping layer between the substrate and the device isolation patterns and between the fin structure and the device isolation patterns. The capping layer has a thickness greater than a thickness of the gate dielectric pattern.

公开(公告)号：US20240274685A1

公开(公告)日：2024-08-15

申请号：US18242399

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： HEUNG-SOON LEE ,  YONGHEE PARK ,  DONG-GWAN SHIN ,  SEOKHOON KIM ,  SEUNGKYU KIM ,  HONGSEON YANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device and a method of manufacturing the same are provided. A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns spaced apart from each other on the lower pattern; a gate structure positioned on the lower pattern and surrounding the sheet patterns; source/drain patterns positioned on both sides of the gate structure, and stacked patterns positioned between the source/drain patterns and the sheet patterns, wherein a stacked pattern includes a first stacked pattern and a second stacked pattern sequentially stacked on a side surface of a sheet pattern, the second stacked pattern including a material different from a material of the first stacked pattern, and a first width of the sheet pattern is smaller than a second width of the gate structure.