公开(公告)号：US12166132B2

公开(公告)日：2024-12-10

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Mintae Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Hyunmog Park ,  Kiseok Lee

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US12029029B2

公开(公告)日：2024-07-02

申请号：US17716215

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Dongsoo Woo ,  Sungwon Yoo

IPC: H10B12/00 ,  H01L29/423 ,  H01L29/792

CPC classification number: H10B12/50 ,  H01L29/4234 ,  H01L29/7926

Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

公开(公告)号：US11670679B2

公开(公告)日：2023-06-06

申请号：US17225716

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L29/00 ,  H01L29/10 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L29/0615 ,  H01L29/7869 ,  H01L29/78642

Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.

公开(公告)号：US20220384661A1

公开(公告)日：2022-12-01

申请号：US17578893

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Kiseok Lee ,  Wonsok Lee ,  Mintae Ryu ,  Hyunmog Park ,  Woobin Song ,  Sungwon Yoo

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

公开(公告)号：US12193343B2

公开(公告)日：2025-01-07

申请号：US17192093

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H10N70/00 ,  H01L29/423 ,  H10B63/00

Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.

公开(公告)号：US12191136B2

公开(公告)日：2025-01-07

申请号：US18098174

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L29/74 ,  H10B12/10

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US20240224494A1

公开(公告)日：2024-07-04

申请号：US18414893

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

公开(公告)号：US11943925B2

公开(公告)日：2024-03-26

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Jaeho Hong ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C8/14 ,  G11C7/18 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L25/065 ,  H10B43/10

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

公开(公告)号：US11917805B2

公开(公告)日：2024-02-27

申请号：US17541584

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

公开(公告)号：US11887648B2

公开(公告)日：2024-01-30

申请号：US17362138

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: H01L29/66 ,  G11C11/39 ,  G11C11/402 ,  H01L29/749 ,  H01L27/102

CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.