公开(公告)号：US20240113077A1

公开(公告)日：2024-04-04

申请号：US18230768

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nara LEE ,  Yeonjin LEE ,  Jimin CHOI ,  Jongmin LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.

公开(公告)号：US20220326301A1

公开(公告)日：2022-10-13

申请号：US17540745

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Yeonjin LEE ,  Minjung CHOI ,  Jimin CHOI

IPC: G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

公开(公告)号：US20210175133A1

公开(公告)日：2021-06-10

申请号：US16898943

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Junyong NOH ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L21/66 ,  H01L21/78

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

公开(公告)号：US20250062193A1

公开(公告)日：2025-02-20

申请号：US18934456

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20240038675A1

公开(公告)日：2024-02-01

申请号：US18313491

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Joongwon SHIN ,  Sungyun WOO ,  Yeonjin LEE ,  Jongmin LEE ,  Sehyun HWANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2223/54426

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.

公开(公告)号：US20230116911A1

公开(公告)日：2023-04-13

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20230077803A1

公开(公告)日：2023-03-16

申请号：US17751740

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jongmin LEE ,  Yeonjin LEE ,  Jeonil LEE ,  Juik LEE ,  Minjung CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.

公开(公告)号：US20230005818A1

公开(公告)日：2023-01-05

申请号：US17574902

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin LEE ,  Jongmin LEE ,  Jeonil LEE

IPC: H01L23/48 ,  H01L27/105 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.

公开(公告)号：US20220223485A1

公开(公告)日：2022-07-14

申请号：US17706401

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Junyong NOH ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L21/66 ,  H01L21/78

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.