公开(公告)号：US20130107629A1

公开(公告)日：2013-05-02

申请号：US13721963

申请日：2012-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil SHIM ,  Jaehoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells. The read/write circuit may be configured to adjust levels of the bias voltages applied to the plurality of bit lines according to location of a selected word line among the plurality of word lines.

Abstract translation: 根据发明构思的示例实施例，非易失性存储器件包括包括多个存储器单元的存储单元阵列; 字线驱动器，被配置为分别选择和取消选择与所述多个存储器单元连接的多个字线中的至少一个，并向所述多个字线提供电压; 以及读/写电路，被配置为向与多个存储单元连接的多个位线施加偏置电压。 读/写电路可以被配置为根据多个字线中所选择的字线的位置来调整施加到多个位线的偏置电压的电平。

公开(公告)号：US20210151461A1

公开(公告)日：2021-05-20

申请号：US16993345

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil SHIM ,  Suhyeong LEE ,  Taisoo LIM

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157

Abstract: A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.

公开(公告)号：US20200013797A1

公开(公告)日：2020-01-09

申请号：US16282701

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil SHIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/56 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises forming on a substrate a mold structure including a plurality of sacrificial patterns and a plurality of dielectric patterns that are alternately stacked, patterning the mold structure to form a plurality of preliminary stack structures extending in a first direction, forming on the preliminary stack structures a support pattern that extends in a direction intersecting the first direction and extends across the preliminary stack structures, and replacing the sacrificial patterns with conductive patterns to form a plurality of stack structures from the preliminary stack structures. The support pattern remains on the stack structures.

公开(公告)号：US20180294274A1

公开(公告)日：2018-10-11

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Sunil SHIM ,  Jaeduk LEE ,  Jaehoon JANG ,  Jeehoon HAN

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

公开(公告)号：US20150357339A1

公开(公告)日：2015-12-10

申请号：US14826814

申请日：2015-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil SHIM ,  Jang-Gn YUN ,  Jeonghyuk CHOI ,  Kwang Soo SEOL ,  Jaehoon JANG ,  Jungdal CHOI

IPC: H01L27/115 ,  H01L23/535

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Abstract translation: 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。