公开(公告)号：US11349066B2

公开(公告)日：2022-05-31

申请号：US17081625

申请日：2020-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Bhagwati Prasad ,  Derek Stewart

IPC: H01L43/02 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14 ,  H01L27/22 ,  G11C11/18 ,  G11C11/16

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

公开(公告)号：US11271009B2

公开(公告)日：2022-03-08

申请号：US16886179

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: H01L27/11585 ,  H01L21/28 ,  H01L29/417 ,  H01L29/51 ,  H01L29/778 ,  G11C11/22

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

公开(公告)号：US10788547B2

公开(公告)日：2020-09-29

申请号：US16250403

申请日：2019-01-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Gerardo Bertero

IPC: G01R33/09 ,  G11C11/16 ,  G11C11/56

Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.

公开(公告)号：US10700093B1

公开(公告)日：2020-06-30

申请号：US16227889

申请日：2018-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: G11C11/22 ,  H01L27/11585 ,  H01L29/417 ,  H01L29/51 ,  H01L29/778 ,  H01L21/28

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.