公开(公告)号：US20210027138A1

公开(公告)日：2021-01-28

申请号：US16880136

申请日：2020-05-21

Applicant: SanDisk Technologies LLC

Inventor： Daniel Bedau ,  Wen Ma

IPC: G06N3/04 ,  H01L47/00 ,  H03B7/00 ,  G06N3/063 ,  G06N3/08

Abstract: A reservoir computing system comprising an input layer configured to receive input data from a signal propagation channel and to convert the input data into fixed input values, a reservoir configured to receive the fixed input values and generate a set of trained output values, and an output layer configured to receive the set of trained output values and generate a probability distribution based on the set of trained output values. The reservoir is comprised of a plurality of integrated oscillator components coupled in a fixed, random network, wherein each of the oscillator components is comprised of a device characterized by a current-voltage curve that comprises a region of non-linear behavior, such as a negative differential resistance (NDR) behavior.

公开(公告)号：US10388646B1

公开(公告)日：2019-08-20

申请号：US15996738

申请日：2018-06-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Derek Stewart ,  Daniel Bedau ,  Michael Grobis ,  Christopher J. Petti

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/24 ,  H01L23/00 ,  H01L49/00 ,  H01L45/00

Abstract: A surge protection device contains a first electrode, a second electrode electrically connected to electrical ground, and a field-induced switching component electrically contacting the first electrode and the second electrode. The field-induced switching component can include a correlated-electron material or a volatile conductive bridge.

公开(公告)号：US11271009B2

公开(公告)日：2022-03-08

申请号：US16886179

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: H01L27/11585 ,  H01L21/28 ,  H01L29/417 ,  H01L29/51 ,  H01L29/778 ,  G11C11/22

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

公开(公告)号：US20210027135A1

公开(公告)日：2021-01-28

申请号：US16880449

申请日：2020-05-21

Applicant: SanDisk Technologies LLC

Inventor： Daniel Bedau ,  Wen Ma

IPC: G06N3/04 ,  H01L47/00 ,  H03B7/08

Abstract: A computing reservoir comprised of a plurality of oscillator components configured to receive input data and produce one or more output signals, and a feedback loop coupled to an output of the network, wherein the feedback loop is comprised of circuitry configured to establish and maintain an optimal operating point of the network based upon the output of the network.

公开(公告)号：US10700093B1

公开(公告)日：2020-06-30

申请号：US16227889

申请日：2018-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: G11C11/22 ,  H01L27/11585 ,  H01L29/417 ,  H01L29/51 ,  H01L29/778 ,  H01L21/28

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

公开(公告)号：US11004508B2

公开(公告)日：2021-05-11

申请号：US16556376

申请日：2019-08-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02

Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.

公开(公告)号：US20200321353A1

公开(公告)日：2020-10-08

申请号：US16886179

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: H01L27/11585 ,  G11C11/22 ,  H01L29/778 ,  H01L29/417 ,  H01L29/51 ,  H01L21/28

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

公开(公告)号：US11355188B2

公开(公告)日：2022-06-07

申请号：US17245651

申请日：2021-04-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02

Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.

公开(公告)号：US11170852B1

公开(公告)日：2021-11-09

申请号：US16910871

申请日：2020-06-24

Applicant: SanDisk Technologies LLC

Inventor： Justin Phillip Kinney ,  Daniel Bedau

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/16

Abstract: Technology for operating cross-bar arrays is disclosed herein. The memory cells may each have a reversible resistivity element and a steering element comprising a diode. The cross-bar array may be operated in read mode and a bipolar programming mode. Selected memory cells may be sensed by operating the steering elements such that sense currents pass through the diodes and any sneak currents are blocked by the diodes. During bipolar programming of selected memory cells, the steering element of the selected memory cells allows current to flow in either direction through the steering element to permit bipolar programming. In some aspects, the steering element has a switch in parallel with the diode. The switches may be opened when sensing selected memory cells to pass sense currents and block sneak currents with the diodes. The switches may be closed during bipolar programming of the selected memory cells to allow bi-directional current flow.

公开(公告)号：US20210065791A1

公开(公告)日：2021-03-04

申请号：US16556376

申请日：2019-08-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C13/00 ,  G11C11/16 ,  H01L27/22 ,  H01L27/24

Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.