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公开(公告)号：US11411170B2
公开(公告)日：2022-08-09
申请号：US17081557
申请日：2020-10-27
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Bhagwati Prasad , Derek Stewart
Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.
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公开(公告)号：US11177284B2
公开(公告)日：2021-11-16
申请号：US16798643
申请日：2020-02-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Peter Rabkin , Masaaki Higashitani , Alan Kalitsov
IPC: H01L27/11597 , H01L21/02 , H01L21/306 , H01L29/778
Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.
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公开(公告)号：US11417379B2
公开(公告)日：2022-08-16
申请号：US17081678
申请日：2020-10-27
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Bhagwati Prasad , Derek Stewart
Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.
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公开(公告)号：US12106790B2
公开(公告)日：2024-10-01
申请号：US17656306
申请日：2022-03-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Derek Stewart , Ananth Kaushik , Gerardo Bertero
CPC classification number: G11C11/161 , G01R33/093 , G11C11/1673 , G11C11/1675 , H01F10/3286 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.
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公开(公告)号：US10957711B2
公开(公告)日：2021-03-23
申请号：US16778245
申请日：2020-01-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bhagwati Prasad , Alan Kalitsov
IPC: G11C11/22 , H01L27/11585 , H01L21/28 , H01L29/417 , H01L29/51 , H01L29/778
Abstract: A ferroelectric device includes a semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric located between the channel region and the gate electrode, and including a plurality of ferroelectric gate dielectric portions having different structural defect densities.
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Patent Agency Ranking
公开(公告)号：US20200321353A1
公开(公告)日：2020-10-08
申请号：US16886179
申请日：2020-05-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Derek Stewart , Daniel Bedau , Gerardo Bertero
IPC: H01L27/11585 , G11C11/22 , H01L29/778 , H01L29/417 , H01L29/51 , H01L21/28
Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.
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公开(公告)号：US12211535B2
公开(公告)日：2025-01-28
申请号：US17656310
申请日：2022-03-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Derek Stewart , Ananth Kaushik , Gerardo Bertero
Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.
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公开(公告)号：US11349066B2
公开(公告)日：2022-05-31
申请号：US17081625
申请日：2020-10-27
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Bhagwati Prasad , Derek Stewart
IPC: H01L43/02 , H01L43/04 , H01L43/06 , H01L43/10 , H01L43/12 , H01L43/14 , H01L27/22 , G11C11/18 , G11C11/16
Abstract: A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.
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公开(公告)号：US11271009B2
公开(公告)日：2022-03-08
申请号：US16886179
申请日：2020-05-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Derek Stewart , Daniel Bedau , Gerardo Bertero
IPC: H01L27/11585 , H01L21/28 , H01L29/417 , H01L29/51 , H01L29/778 , G11C11/22
Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.
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公开(公告)号：US10788547B2
公开(公告)日：2020-09-29
申请号：US16250403
申请日：2019-01-17
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Derek Stewart , Gerardo Bertero
Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.
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