公开(公告)号：US11271009B2

公开(公告)日：2022-03-08

申请号：US16886179

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: H01L27/11585 ,  H01L21/28 ,  H01L29/417 ,  H01L29/51 ,  H01L29/778 ,  G11C11/22

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

公开(公告)号：US10788547B2

公开(公告)日：2020-09-29

申请号：US16250403

申请日：2019-01-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Gerardo Bertero

IPC: G01R33/09 ,  G11C11/16 ,  G11C11/56

Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.

公开(公告)号：US10700093B1

公开(公告)日：2020-06-30

申请号：US16227889

申请日：2018-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: G11C11/22 ,  H01L27/11585 ,  H01L29/417 ,  H01L29/51 ,  H01L29/778 ,  H01L21/28

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

公开(公告)号：US12211535B2

公开(公告)日：2025-01-28

申请号：US17656310

申请日：2022-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Ananth Kaushik ,  Gerardo Bertero

IPC: G11C11/16 ,  G01R33/09 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.

公开(公告)号：US12106790B2

公开(公告)日：2024-10-01

申请号：US17656306

申请日：2022-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Ananth Kaushik ,  Gerardo Bertero

IPC: G11C11/16 ,  G01R33/09 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  G01R33/093 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3286 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.

公开(公告)号：US20200321353A1

公开(公告)日：2020-10-08

申请号：US16886179

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alan Kalitsov ,  Derek Stewart ,  Daniel Bedau ,  Gerardo Bertero

IPC: H01L27/11585 ,  G11C11/22 ,  H01L29/778 ,  H01L29/417 ,  H01L29/51 ,  H01L21/28

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.