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    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME
    13.
    发明申请
    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME 有权

    公开(公告)号：US20230127904A1

    公开(公告)日：2023-04-27

    申请号：US17821659

    申请日：2022-08-23

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Shingo TOTANI ,  Kensuke ISHIKAWA ,  Fumitaka AMANO

    IPC分类号： H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/522

    摘要： A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

    MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE WITH NESTED CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
    15.
    发明申请
    MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE WITH NESTED CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20220130852A1

    公开(公告)日：2022-04-28

    申请号：US17081458

    申请日：2020-10-27

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Yuji TOTOKI ,  Fumitaka AMANO

    IPC分类号： H01L27/11582 ,  H01L23/522

    摘要： A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer.

    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME
    16.
    发明申请
    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME 有权

    公开(公告)号：US20230129594A1

    公开(公告)日：2023-04-27

    申请号：US17566262

    申请日：2021-12-30

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fumitaka AMANO

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/535

    摘要： A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME
    17.
    发明申请
    HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME 有权

    公开(公告)号：US20230128326A1

    公开(公告)日：2023-04-27

    申请号：US17509323

    申请日：2021-10-25

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Fumitaka AMANO ,  Kensuke ISHIKAWA

    IPC分类号： H01L21/768 ,  H01L23/532

    摘要： A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.

    SEMICONDUCTOR DEVICE CONTAINING TUBULAR LINER SPACER FOR LATERAL CONFINEMENT OF SELF-ALIGNED SILICIDE PORTIONS AND METHODS OF FORMING THE SAME
    20.
    发明申请
    SEMICONDUCTOR DEVICE CONTAINING TUBULAR LINER SPACER FOR LATERAL CONFINEMENT OF SELF-ALIGNED SILICIDE PORTIONS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210280686A1

    公开(公告)日：2021-09-09

    申请号：US16809798

    申请日：2020-03-05

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Fumitaka AMANO ,  Yosuke KITA

    IPC分类号： H01L29/66 ,  H01L29/45 ,  H01L29/78

    摘要： A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.