公开(公告)号：US20230328984A1

公开(公告)日：2023-10-12

申请号：US18060732

申请日：2022-12-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki FUJIMURA ,  Takashi KUDO ,  Shunsuke TAKUMA ,  Satoshi SHIMIZU

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.

公开(公告)号：US20220336486A1

公开(公告)日：2022-10-20

申请号：US17233799

申请日：2021-04-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keigo KITAZAWA ,  Naoto NORIZUKI ,  Shunsuke TAKUMA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/24 ,  H01L27/11597

Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

公开(公告)号：US20240260266A1

公开(公告)日：2024-08-01

申请号：US18356896

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Takashi KASHIMURA ,  Tomohiro KUBO ,  Hisakazu OTOI ,  Hiroyuki TANAKA ,  Takumi MORIYAMA ,  Ryota SUZUKI

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.

公开(公告)号：US20240099014A1

公开(公告)日：2024-03-21

申请号：US18524552

申请日：2023-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Yuji TOTOKI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Kengo KAJIWARA ,  Akihiro TOBIOKA

IPC: H10B43/50 ,  H01L23/00 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US20220230917A1

公开(公告)日：2022-07-21

申请号：US17153972

申请日：2021-01-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka AMANO ,  Yuji TOTOKI ,  Shunsuke TAKUMA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack that underlies the retro-stepped dielectric material portion. Some of the pillar-shaped contact-opening assemblies can include a first conductive plug that laterally contacts a cylindrical sidewall of a respective one of the electrically conductive layers and a conductive via structure that contacts a top surface of the first conductive plug.

公开(公告)号：US20220223614A1

公开(公告)日：2022-07-14

申请号：US17146866

申请日：2021-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Yuji TOTOKI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Kengo KAJIWARA ,  Akihiro TOBIOKA

IPC: H01L27/11575 ,  H01L23/522 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US20220139758A1

公开(公告)日：2022-05-05

申请号：US17090368

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Makoto TSUTSUE ,  Shunsuke TAKUMA

IPC: H01L21/687 ,  C23C16/455 ,  H01L21/02 ,  H01L21/67

Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.

公开(公告)号：US20210358936A1

公开(公告)日：2021-11-18

申请号：US17036070

申请日：2020-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Kengo KAJIWARA

IPC: H01L27/11575 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.