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    CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES
    11.
    发明申请
    CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES 有权

    公开(公告)号：US20210358553A1

    公开(公告)日：2021-11-18

    申请号：US17360572

    申请日：2021-06-28

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

    Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

    Programming to minimize cross-temperature threshold voltage widening
    15.
    发明授权
    Programming to minimize cross-temperature threshold voltage widening 有权

    公开(公告)号：US10978145B2

    公开(公告)日：2021-04-13

    申请号：US16540862

    申请日：2019-08-14

    Applicant: SanDisk Technologies LLC

    Inventor： Biswajit Ray ,  Peter Rabkin ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

    IPC: G11C11/56 ,  G11C11/408 ,  G11C11/407 ,  G11C11/406 ,  G11C11/4074

    Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

    State adaptive predictive programming
    16.
    发明授权
    State adaptive predictive programming 有权

    公开(公告)号：US10748622B2

    公开(公告)日：2020-08-18

    申请号：US16283464

    申请日：2019-02-22

    Applicant: SanDisk Technologies LLC

    Inventor： Lei Lin ,  Zhuojie Li ,  Tai-Yuan Tseng ,  Henry Chin ,  Gerrit Jan Hemink

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

    SINGLE PULSE VERIFICATION OF MEMORY CELLS
    17.
    发明申请
    SINGLE PULSE VERIFICATION OF MEMORY CELLS 审中-公开

    公开(公告)号：US20190252030A1

    公开(公告)日：2019-08-15

    申请号：US15963647

    申请日：2018-04-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Jianzhi Wu ,  Gerrit Jan Hemink

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

    Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.

    MULTI-STATE AND CONFINED PHASE CHANGE MEMORY WITH VERTICAL CROSS-POINT STRUCTURE
    20.
    发明申请
    MULTI-STATE AND CONFINED PHASE CHANGE MEMORY WITH VERTICAL CROSS-POINT STRUCTURE 审中-公开

    公开(公告)号：US20190115071A1

    公开(公告)日：2019-04-18

    申请号：US15869553

    申请日：2018-01-12

    Applicant: SanDisk Technologies LLC

    Inventor： Federico Nardi ,  Christopher J. Petti ,  Gerrit Jan Hemink

    IPC: G11C13/00

    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

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